On the 68HC11 Family, it is usually half the bus speed.

Yes.  Take a look at the file asm32vec.txt for the complete description and listing.

The TPU2 and TPU3 emulation memory is broken up into 2k segments. So, you need to be sure that you do not write code that overlaps this boundary even if you have a total of 6k or 8k of TPU memory. What you need to do is that at the start of your *.asc file, you assign some of your functions to bank0, some to bank1, etc. You do this with the '%org 0,0.' for bank 0 and '%org 0,1.' for bank 1. You also need to remember that the entry points for each bank take up 288 bytes. This only gives you 2048-288=1760 bytes in each bank.

These are the correct functions and the appropriate codes for the TPU functions on the HC916Y3.
 

0. SIOP
1. SPWM
2. DIO
3. PWM
4. OC
5. PPWA
6. FQD
7. MCPWM
8. HALLD
9. COMM
A. NITC
B. UART
C. FQM
D. TSM
E. QOM
F. PTA

No. The max. pullup current on the data pins, when drive low at reset, is 120uA. If a 10k is used, there will a drop across the resistor that will raise the input above 1.0V (Min. low input). A 1k is better, but this will load the data bus beyond operating spec. when driven high. The max. source current is 800uA, which will be exceeded when the data pin is driven high.

The interrupt vector locations for the MSCAN on the MC68HC912 MCUs are:

$FFD0..$FFD1 - MSCAN Wakeup,
$FFC8..$FFC9 - MSCAN Errors,
$FFC6-$FFC7 - MSCAN Rcv.,
$FFC4..$FFC5 - MSCAN Trans.

This is because there MUST be some time delay between each line of the .s19 file that is being programmed. You can do this one of two ways. The way that you do choose depends on the terminal program that you use. When each line of the .s19 file has been successfully programmed, the Bootloader will send a '*' to the terminal. You can select character delay in some terminal programs that will look for this character, and when it sees it, the terminal SW will transmit the next line of data. If you do not have this capability, you will need to use line delay. If you have not used the flash all that much, you can set this value for about 5 ms. As the flash is used more, you may need to increase this number. The way you can tell is if you are not getting a complete reprogram of the flash, like before the addition of the delay.

Yes. The documentation is incorrect. The MODA bit can be written after a reset in normal modes. If the HC11F1 is reset into single chip mode, MODA bit in the HPRIO needs to be set to change to expanded mode. If the HC11F1 is reset into expanded mode, then the MODA bit needs to be cleared.

RSTCONF must be pulled high. This will cause the MPC555 to try to use the internal configuration word (CFMCFIG) since the default value of the HC bit is '0'. So, you will need to use a debugger to reprogram the CFMCFIG register so that the HC bit is '0', and all of the other bits you need are programmed for your application. When you reset the device after programming the CFMCFIG, the MPC555 will use the configuration word that is in the CFMCFIG. Then you should be able to reprogram the flash using the debugger.

During reset and just after reset (before the TPU channels are programmed) the TPU pins are configured as inputs.

It is pin 84. It is marked as Vdd in the documentation.

This specific mode of operation does not work for the timer. The workaround for this problem is to use channel 3 to set the period (16-bits of range here) and use another channel to set the duty cycle. Have channel 3 toggle on overflow and have the other channel clear on compare. This will not only give you a high degree of freedom (width and resolution) in selecting your period and duty cycle, but also the prescaler DOES work in this scenario to allow the output of a low frequency signal.

No. These numbers were very preliminary and absolute worst case maximums. In reality, one should see on the order of 2 mA per MHz operating frequency at 3.3V for IDD. IDDF, if operating out of internal FLASH, and IDDSYN will draw less than 5 mA across the frequency range at 3.3V.

You have two options - you can connect directly between a comm port on your PC and J58 on the CMB, or you can connect between a comm port on your PC and the Enhanced Background Debug Interface (EBDI) connected to the OnCE port on the CMB. If using the former approach, make sure you configure the DIP switches on the CMB for internal boot and set the USR switches to boot up the on-board FLASH programming firmware. This setting is: USR2 = off, USR1 = off, and USR0 = on. The other switches should be set to the on position. If connecting to the OnCE port for communication, then make sure the DIP switches are set to boot internal. The USR switches are don't-care, and set the remaining switches to on.

The easiest way to do this is through the EBDI/OnCE port communication channel. Using this channel does not require any on-board programming firmware as is the case when you program the FLASH on the CMB board while communicating over J58. A bigger requirement to using this programming utility to program your target's FLASH is that you must have about 32k of available external RAM mapped at 0x81000000. This is where the programming routines get loaded.

No. Bus speed should be limited to around 20 MHz. The limiting factors are the Data-in valid to CLKOUT high read (read data setup) time of 22 ns (min), no. 24 in figure 22-2 in the MMC2107 data book, coupled with the 10 ns max for the CLKOUT high to address valid time, no. 6 in figure 22-2. Combining these two times yield 32 ns, which at this point would require 0 ns access time for the peripheral. Running the external bus at 20 MHz, resulting in a CLKOUT of 50 ns, allows at least 18 ns of access time.

In the Mcore linker section of the Codewarrior Base Project Settings, try specifying the maximum length of the s records to be no more than 240, then rebuild.

The EPORT provides eight of the 40 possible interrupt sources on the MMC2107. These eight sources, triggered by transitions on pins INT0 to INT7, can be prioritized the same way that the other 32 interrupts are. That is, each interrupt source is assigned a priority through its Priority Level Select Register (PLSR) with a value from 0 to 31, with 0 being the lowest priority. When an EPORT interrupt occurs, the priority level bit set for that pin will have the corresponding bit set in the Interrupt Pending Register (IPR). The EPORT interrupts can, of course, all have the same priority level, and in fact be serviced by a common interrupt service routine.

Yes. CPHA must be set to one to operate the SPI without a Slave Select.

Yes. The databus does not have any internal pull-ups or pull-downs to automatically select a default configuration. Therefore, when the RCON is going to be asserted, ALL pins involved in setting the chip configuration needs to be set to the appropriate polarity for the specific application.

When writing to the SPICR register, in some cases the data that is loaded into the internal counter is incorrect for each ISPI interval. However, the register which latches the data written functions properly. Reading back the register returns the correct value.  The bits affected by this problem are bits 5, 6, 7, 10 and 11.  The following behavior occurs when setting one or more of these bits.

• Writing 0x20 (bit 5) actually loads 0x60 (bits 5 and 6) into the interval counter.
• Writing 0x40 (bit 6) actually loads 0x80 (bit 7 only) into the interval counter.
• Writing 0x80 (bit 7) actually loads nothing into the interval counter.
• Writing 0x400 (bit 10) actually loads 0xC00 (bits 10 & 11) into the interval counter.
• Writing 0x800 (bit 11) actually loads nothing into the interval counter.

Crystal Gain on MC68HCF1 on the following mask sets is not as strong at the 68HC08 or 68HC12 families: F43V,E87J,C94R. The Technical Data Manual suggest a 10 Mega Ohm resistor in parallel with the crystal. This should be reduced to 1 MOhm resistor. It is important to remember that crystal impedance various from crystal manufacture to manufacturer. It is recommended to make sure that the impedance is appropriate for your component.

The MMC2001 uses a peripheral bus that requires 32-bit accesses for many of the registers. Throughout the data manual you will see the sentence "Access this register with 32-bit loads and stores only". When "ITCSR.EN = 1" is changed to "ITCSR = 0x01", the access will be successful. What is happening is that the assembly code for "ITCSR.EN = 1" generated by the compiler uses a byte access to set a single bit, whereas the form "ITCSR = 0x01" makes a 32-bit access to change the entire register.

NO.

If the BGACK pin is asserted, the CPU will halt when an external bus access is attempted.  The CPU will simply stall until BGACK is released to a logic 1.

On devices that use a Single Chip Integration Module (SCIM), the Bus Grant Acknowlege Pin is always enabled as that function as opposed to CSE, its alternate function.  Software can be used to change the function of the pin to CSE, even in Single Chip Mode.

If an attempt to place an M68HC16 or M68300 device in BDM mode is made and the Bus Grant Acknowledge pin is asserted, the device will enter the BDM mode but all BDM commands will cause the internal bus to stall. The stall occurs because accesses by the CPU to the BDM state machine appear as 'EXTERNAL' bus cycles.

To prevent this problem from occurring, a pull-up resistor must always be connected to the BGACK pin.  The BGACK pin, as well as the BR (Bus Request) pin, should never be allowed to float.

The Software Watchdog is controlled via the System Protection Control Register (SYPCR).
Bits 6, 5 and 4 of this register are used to control the time out period.  The initial value of bit 6, the SWP bit, is the inverse of the logic level on the MODCK pin at the release of reset.  The initial values of bits 5 and 4 are logic 0’s.  All of these bits can be modified with software.

When these bits are modified by software, the change in Software Watchdog Time Out Period does not take place immediately.  The change takes place on the next
negative edge of the clock signal driving the Software Watchdog Timer after a "write 55, write AA" sequence is performed in software.

In other words, if the applications software simply writes to the SYPCR register, modifying the Watchdog Time Out Period, but does not perform a "write 55, write AA" sequence, the watchdog period will not change.

Yes.  Take a look at the file asm16vec.txt for the complete description and listing.

Please ensure that both PBMOR and C12MOR are addressed in your .ASM file. Even if you do not intend to use any of the mask options, you should still ORG at these two addresses and FCB (form constant bytes) of $00 (or whatever value). It is always possible that an external programmer might copy $FF to these locations if left unaddressed.

1. There are some pinout differences in the PLCC package between the C8A and C9A. For C8A target compatibility, the C9A PLCC should have pins 3-4, 17-18 and 39-40 connected together.
2. The "typical" Idd supply currents may vary between C8A and C9A.
3. Is the window on the windowed part covered during operation and programming?The window should only be uncovered when erasing the part.

RSTCONF must be pulled high. This will cause the MPC555 to try to use the internal configuration word (CFMCFIG) since the default value of the HC bit is '0'. So, you will need to use a debugger to reprogram the CFMCFIG register so that the HC bit is '0', and all of the other bits you need are programmed for your application. When you reset the device after programming the CFMCFIG, the MPC555 will use the configuration word that is in the CFMCFIG. Then you should be able to reprogram the flash using the debugger.

During reset and just after reset (before the TPU channels are programmed) the TPU pins are configured as inputs.

It is pin 84. It is marked as Vdd in the documentation.

Yes. The documentation is incorrect. The MODA bit can be written after a reset in normal modes. If the HC11F1 is reset into single chip mode, MODA bit in the HPRIO needs to be set to change to expanded mode. If the HC11F1 is reset into expanded mode, then the MODA bit needs to be cleared.

This is because there MUST be some time delay between each line of the .s19 file that is being programmed. You can do this one of two ways. The way that you do choose depends on the terminal program that you use. When each line of the .s19 file has been successfully programmed, the Bootloader will send a '*' to the terminal. You can select character delay in some terminal programs that will look for this character, and when it sees it, the terminal SW will transmit the next line of data. If you do not have this capability, you will need to use line delay. If you have not used the flash all that much, you can set this value for about 5 ms. As the flash is used more, you may need to increase this number. The way you can tell is if you are not getting a complete reprogram of the flash, like before the addition of the delay.

NO.

In the QSM the interrupt vector number is written into the QILR-QIVR register at $FF FC04. The default value for this register is $000F. $F specifies the Uninitialized Vector in the Interrupt Vector Table.

When initializing the INTV field, it is important to realize that bit 0 is actually ignored. When the SCI causes an interrupt, bit 0 of the QILR-QIVR register will be read as a logic 0. When the SPI causes an interrupt, bit 0 of the QILR-QIVR register will be read as a logic 1.

Assume that the vector number 64 (Vector Offset = $100) is written to the INTV field. Then the SCI would use vector number 64 (Vector Offset = $100) and the SPI would use vector number 65 (Vector Offset = $101).

However, the same results would be obtained if the vector number 65 (Vector Offset = $101) is written to the INTV field. Once again, the SCI would use vector number 64 (Vector Offset = $100) and the SPI would use vector number 65 (Vector Offset = $101), not vector number 66 (Vector Offset = $102).

Once again, the QSM hardware drives bit 0 of the INTV field. Bit 0 of the actual register is ignored.

The consequences of writing vector number 65 to the INTV field is that the software writer may assume that vector numbers 65 and 66 are being used. The fact is that vector numbers 64 and 65 will be used. When this particular programming error is made, i.e., using an odd number in the INTV field, the SCI will appear to take the wrong vector.

The interrupt vector locations for the MSCAN on the MC68HC912BC32 are:

• $FFD0..$FFD1 - MSCAN Wakeup,
• $FFC8..$FFC9 - MSCAN Errors,
• $FFC6-$FFC7 - MSCAN Rcv.,
• $FFC4..$FFC5 - MSCAN Trans.

In most cases, yes.

The PTP bit is located in the Periodic Interrupt Timing Register at location $YFFA24. (Y is not used for the M68HC16 and should be treated as though it were an $F. Y can be $7 or $F for the M68300 family depending upon the setting of the MM bit in the Module Configuration Register of the SIM or SCIM.) It is used to either enable or disable a "divide by 512" prescaler for the Periodic Interrupt Timer (PIT).

In the early versions of the M68300 and M68HC16 families, the PTP bit could be written at any time. However, the functionality of the bit has changed.

On virtually all M68300 and M68HC16 family members, the PTP bit has been changed to a "write once" bit. For all future designs with either of these microcontroller families, the PTP bit should be treated as a "write once" bit.

You can reprogram in the application programming. This can be done by loading new user vectors and a new user monitor at the end of the Flash array. Use the SCI port to communicate to the part rather than PTA0. Remember to program the Flash Block Protection Register to protect the new monitor and vectors. Also note that since you are protecting part of the Flash array, you can no longer perform a bulk erase.

Yes. Use a method where each time you write data to the Flash, you use a different portion of the page (128 bytes). When this page is full, perform a page erase. By doing this, it will only count as 1 program erase cycle (Flash is guaranteed for 10,000 program erase cycles). To extend this even further, use multiple pages.

Crystal Frequency	Internal Bus Frequency	Baud Rate
4.9152 MHz	1.2288 MHz	4800
9.8304 MHz	2.4576 MHz	9600
14.7456 MHz	3.6864 MHz	14400
19.6608 MHz	4.9152 MHz	19200
29.4912 MHz	7.3728 MHz	28800

2000Aug14

No. The relationship is fixed to a divide by 4. The internal bus frequency will be 1/4 of the external oscillator frequency.

No. The Flash does not require a high voltage for programming. However, if the part has been previously programmed, a high voltage is required on the /IRQ pin to place the part into monitor mode. This high voltage has nothing to do with the Flash programming. It is used to put the part into monitor mode once the reset vectors have been programmed.

Divide by 2 option (PTC2 driven by ICS or Vss):
 

Crystal Frequency	Internal Bus Frequency	Baud Rate
2.4576 MHz	1.2288 MHz	4800
4.9152 MHz	2.4576 MHz	9600
7.3728 MHz	3.6864 MHz	14400
9.8304 MHz	4.9152 MHz	19200
14.7456 MHz	3.6864 MHz	28800

Divide by 4 option (PTC2 at Vdd):
 

Crystal Frequency	Internal Bus Frequency	Baud Rate
4.9152 MHz	1.2288 MHz	4800
9.8304 MHz	2.4576 MHz	9600
14.7456 MHz	3.6864 MHz	14400
19.6608 MHz	4.9152 MHz	19200
29.4912 MHz	7.3728 MHz	28800

Crystal Frequency	Internal Bus Frequency	Baud Rate
4.9152 MHz	1.2288 MHz	4800
9.8304 MHz	2.4576 MHz	9600
14.7456 MHz	3.6864 MHz	14400
19.6608 MHz	4.9152 MHz	19200
29.4912 MHz	7.3728 MHz	28800

2000Aug14

Divide by 2 option (PTB3 driven by ICS or Vss):
 

Crystal Frequency	Internal Bus Frequency	Baud Rate
2.4576 MHz	1.2288 MHz	4800
4.9152 MHz	2.4576 MHz	9600
7.3728 MHz	3.6864 MHz	14400
9.8304 MHz	4.9152 MHz	19200
14.7456 MHz	3.6864 MHz	28800

Divide by 4 option (PTB3 at Vdd):
 

Crystal Frequency	Internal Bus Frequency	Baud Rate
4.9152 MHz	1.2288 MHz	4800
9.8304 MHz	2.4576 MHz	9600
14.7456 MHz	3.6864 MHz	14400
19.6608 MHz	4.9152 MHz	19200
29.4912 MHz	7.3728 MHz	28800

No. The relationship is fixed to a divide by 4. The internal bus frequency will be 1/4 of the external oscillator frequency.

The PTB3 pin determines if the external oscillator frequency is divided by two or four to drive the internal bus frequency. If PTB3 is low, the external oscillator frequency is divided by two. If PTB3 is high, the internal bus frequency is 1/4 of the external oscillator frequency.

Divide by 2 option (PTC3 driven by ICS or Vss):
 

Crystal Frequency	Internal Bus Frequency	Baud Rate
2.4576 MHz	1.2288 MHz	4800
4.9152 MHz	2.4576 MHz	9600
7.3728 MHz	3.6864 MHz	14400
9.8304 MHz	4.9152 MHz	19200
14.7456 MHz	3.6864 MHz	28800

Divide by 4 option (PTC3 at Vdd):
 

Crystal Frequency	Internal Bus Frequency	Baud Rate
4.9152 MHz	1.2288 MHz	4800
9.8304 MHz	2.4576 MHz	9600
14.7456 MHz	3.6864 MHz	14400
19.6608 MHz	4.9152 MHz	19200
29.4912 MHz	7.3728 MHz	28800

The fault pins cannot be disconnected from the PWM outputs. This was done for regulatory safety reasons. Many (if not most) of the regulatory agencies take a dim view of systems where fault protection can be disabled by software.

The f_NOM is 4.9152Mhz. The MC specification has been corrected.

The A/D on the MC68HC908MR family can not be triggered by the hardware on the PWM module. The MR family A/D's are triggered just like those on the MC68HC05P, etc. family.

We have a gang programmer. Please find the part # below:

The gang programmer platform board M68HC705UGANG and adaptors for different packages are:

40 DIP-P M68UPA08GP32P40
44 QFP-FB M68UPA08GP32FB44
42 SDIP-B M68UPA08GP32B42

Maximum 10 adaptors can be put on the platform board. It is a stand alone programmer, not PC connection. You need to program the customer code into a EPROM first. The gang programmer will then read the data from the EPROM and program it into the GP32 MCUs.

Yes.

The documentation for the DRV bit of the ISPI Control Register says that this bit is normally used to configure the SPI_CLK, SPI_EN and SPI_MOSI pins as either "open-drain" or totem pole outputs. The DRV bit actually only works correctly for the SPI_CLK and SPI_MOSI pins.

The SPI_EN bit always operates in the "open-drain" mode!

If one wants an active LOW on the SPI_EN pin, a light external pull-up is required, 10k is sufficiant.

If one wants an active HIGH on the SPI_EN pin, an external pull-down is required.

As an additional note, the SNS bit and the SPI_EN bit should always be the same value.

The PTC2 pin determines if the external oscillator frequency is divided by two, or four to derive the internal bus frequency. If PTC2 is low, the external oscillator frequency is divided by two. If PTC2 is high, the internal bus frequency is 1/4th of the external oscillator frequency.

Forced monitor mode requires that the Flash in the MCU be blank (erased state) and no high programming voltage (Vtst) is required on the /IRQ pin. The normal monitor mode requires a high voltage (Vtst) on the /IRQ pin and other I/O pin conditions must be met (see monitor mode entry table requirements in the Technical Data Manuals for the particular part you are using).

Yes. The part must be blank (erased) and you must use an appropriate oscillator to get a working baud rate. Use the J2 connector on the ICS, which uses only the Gnd and PTB0 connections.

No. In order to enter forced monitor mode, it requires Vdd on /IRQ & /RST. The M68ICS08MP drives both of these signals to Vtst.

The PTC3 pin determines if the external oscillator frequency is divided by two or four to drive the internal bus frequency. If PTC3 is low, the external oscillator frequency is divided by two. If PTC3 is high, the internal bus frequency is 1/4 of the external oscillator frequency.

The data stored in the interrupt vectors at $FFF6 - $FFFD comprises the security bytes.

    The answer is indeterminate.  However, in general, simply stopping the clock will NOT put the part in a state with the lowest power consumption.  In order to get the STOP mode current, a STOP instruction must be executed.

    Particularly in the older HCMOS designs, the software tools for finding "floating nodes" and "driver conflicts" did not exist.  Therefore, it is possible in parts designed before these tools were available to still have some floating nodes.  A floating node will cause unwanted current consumption.

    To restate, the only way to guarantee STOP MODE current is to execute a STOP instruction.  Stopping the clock is NOT guaranteed to produce a state that will give STOP mode current.

The Load Floating Point Single Precision instruction is used to fetch a floating point single precision number from an Effective Address. The number is converted to floating point double precision and placed in a floating point register, frD.

If the single precision number is out of range, a floating point assist exception will be taken. The number will not be converted to double precision nor will any results be written into the destination register for the instruction.

Recall that the range of operands for the LFS instuction is 2^-126 to 2E¹²⁸ - 1. If the operand of the LFS instruction is between 2^-150 to 2^-126, a Floating Point Assist Exception will be taken.

Some programmers have interpreted the LFS instruction to take any single precision floating point number, even if the number is out of range as described above, convert it to double precision and then load the result into the destination register. The instruction does not work this way.

    To use a DASM (Double Action Submodule) channel of the Configurable Timer Module (CTM) in the OPWM mode, it is imperative that all registers for the function be initialized with the DASM channel operating in the DIS (Disable) mode.  Failure to properly initialize the part can result in invalid and unexpected output compare and input capture results and flags being set incorrectly.  After initializing the DASM channel's associated registers, the DASMISC register can be programmed to select the OPWM mode.

    The proper method for using the DASM function is to select the DIS mode.  Then, initialize the associated registers.  Once this is done, the DASM Status/Interrupt Control Register can be written.  The FORCE A and FORCE B bits and the MODE bits of this register are used to force the output of the DASM channel to a predefined state and at the same time enable the desired mode of operation.  Failure to follow this procedure can randomly cause the output of the DASM channel to remain permanently high or permanently low.

To restate, when using the DASM channel in the OPWM mode:

1. Program the DASMxSIC register  to enter the DIS mode.
2. Initialize all registers for the DASM channel.
3. Write the DSAMxSIC channel for OPWM mode and set the FORCE A and FORCEB bits appropriately.

No, the communications protocol selection should not be changed without closing and restarting the utility. The desired protocol can then be selected.

Yes, this programming is possible. It has been a misconception that the Chip Select lines on the SCIM (Single Chip Integration Module) used on the MC68300 and MC68HC16 families of microcontrollers can only be programmed to assert on Supervisor Space Only, User Space Only, Supervisor and User Space or CPU Space. The chip select lines have additional flexibility.

MC68300 CPU Space Chip Select Settings

Supervisor Program Space
Supervisor Data Space
Supervisor (Program and Data) Space

User Program Space
User Data Space
User (Program and Data) Space

(Supervisor and User) Program Space
(Supervisor and User) Data Space
(Supervisor and User) (Program and Data) Space

This programming is accomplished in the following way. When the SPACE FIELD of a Chip Select Option Register is programmed to %00, the IPL field specifies which interrupt level will be used to make the associated CS line assert during an IACK cycle. However, if the SPACE FIELD of a Chip Select Option Register is programmed to %01 (USER), %10 (Supervisor) or %11 (Supervisor and User), the IPL field encoding takes on a different meaning. The codings are as follows: %000 - Data/Prog Space, %001 - Data Space, %010 - Program Space, %011 and %100 are reserved for future use, %101 - Data Space, %110 - Program Space, and %111 is reserved for future use.

HC16 CPU Space Chip Select Settings(Note: CPU16 supports only SUPERVISOR SPACE and not USER SPACE.)

Supervisor Program Space
Supervisor Data Space
Supervisor (Program and Data) Space

This programming is accomplished in the following way. When the SPACE FIELD of a Chip Select Option Register is programmed to %00, the IPL field specifies which interrupt level will be used to make the CS line assert during an IACK cycle. However, if the SPACE FIELD of a Chip Select Option Register is programmed to %10 Supervisor or %11 Supervisor, the IPL field encoding takes on a different meaning. The codings are as follows: %000 - Data/Prog Space, %001 - Data Space, %010 - Program Space, %011 and %100 are reserved for future use, %101 - Data Space, %110 - Program Space, and %111 is reserved for future use.

While this data is presented in the SCIM USERS MANUAL (Single Chip Integration Module - document # SCIMRM/AD), it is being repeated here for clarity and emphasis.

The Clock Out Pin of the MPC555 behaves in the following way under various reset conditions:

1. From a power on reset, LIMP CLOCK can be either enabled or disabled.
2. If LIMP CLOCK is enabled, the System Clock will be immediately driven out on the Clock Out pin during a Power On Reset.
3. If LIMP CLOCK is disabled, the System Clock will be driven out after the POR Reset is released, providing that the PLL is locked.

When an MPC555 (Rev. K or later) or any MPC500 family derivative is totally erased, the CMFCFIG (shadow row location 0) and the flash array will be erased. In this condition, the Flash Array and the Shadow Row 0 Bits must be programmed. This programming proceedure is generally done through the BDM port. In order to properly initialize the device so that the BDM port is enabled, a Configuration Word must be supplied from some source. The sources are:

1. the CMFCFIG (shadow row location 0),
2. the default Configuration Word of 0x00000000
3. an external Configuration Word.

If the RSTCONFIG pin is driven to a logic 1, thedevice will attempt to use the Default Configuration Word or the CMFCFIGfor the Configuration Word.

If the CMFCFIG Bits are erased and RSTCONFIG = 1,the Has Configuration bit will indicate that no ConfigurationWord is available from CMFCFIG. Therefore, only the Default ConfigurationWord of 0x00000000 can be used.

If the RSTCONFIG pin is driven to a logic 1 and the Has Configuration bit indicates that the CMFCFIG does contain the configuration information, the Configuration Word would come from the CMFCFIG.

When using the Default Configuration Word of $00000000, the Flash Array will be disabled. However, the BDM port will be enabled. This does not mean that the Background Mode has been entered, it means that it is possible to enter the Background Mode. If the BDM mode is not enabled after the release of Reset, the Background Mode cannot be entered later. The BDM tool can run a macro to enable and enter the BDM mode.

If the flash is not enabled by the Reset Config Word (Bit 20 = 1 of external Config. Word or Bit 20 = 0 of Flash Shadow Reset Config), the flash must be enabled by ORing $800 into the IMMR SPR 638. This enables the flash and it will be available for programming.

     A problem that can occur when writing TPU microcode is that an input channel will fail to recognize incoming edges.  Manytimes, the symptom will be that the first incoming edge is recognized but no edges are recognized on a channel after that.  Executing the same microcode on another channel will sometimes solve the problem.  This problem has been observed on about 1 out of each 10,000 units.

This problem can possibly occur when the following conditions are met:

1. The ME bit of the entry point is a logic 0 (matches disabled)
2. A "match event" occurs during the state. (The event will not be recognized.)
3. In the last instruction of the state there is a "write_mer" but not a "neg_mrl". This Statement will have an "end".

     Normally, the "write_mer" would cause a match event to be scheduled in the future, thus preventing a match from occuring immediately. However, a "write_mer" by itself in the last instruction of the state under the conditions described above can, under rare occassions, cause the Match Recognition Latch which was set in the current TPU state to be recognized as a new match and cause a "request for service".

In general practice, include "neg_mrl" with a "write_mer".
If a "write_mer" occurs in the last instruction of a state, always include a "neg_mrl" in that instruction.

YES.

The software watchdog on MC683xx and MC68HC16 devices is used to detect improperly operating software. The software watchdog is enabled from the release of external reset. That is, the SWE bit (bit 7 of the system protection control register at $xxFA21) is set to a logic 1 automatically.

The software watchdog counter will be reset to its maximum value when the system software writes the value $55 followed by $AA to the software watchdog service register (SWSR) at $xxFA27. If the software watchdog is not reset at appropriate intervals, it will decrement to $0000 and cause a software watchdog reset which is equivalent to a hardware reset.

There are some hardware considerations that limit the rate at which software watchdog reset sequences can occur.

Specifically, when a write $55, write $AA sequence is written to the SWSR, the actual reseting of the software watchdog counter does not occur until the next falling edge of the software watchdog clock. Once the software watchdog counter reset sequence is performed, further attempts to perfom either a software watchdog reset sequence or change the software watchdog time out period are inhibited for the clock low time of the software watchdog clock period immediately following an actual reset of the watchdog counter.

Therefore, for proper and predictable operation of the software watchdog, do not update the SWSR at a rate which is more often than twice the period of the software watchdog counter clock source.

The following table is a list of various MC68HC16 and MC68300 Family devices that show which mask sets use either the Normal Stability Operating Environment Filter (Fig. 1) or the High Stability Operating Environment Filter Circuit (Fig. 2). It is important to use the proper filter with each mask set. Using the Normal Operating Environment Filter on microcontrollers that require the High Stability Operating Environment filter may result in excessive jitter in the system clock frequency. Using the High Stability Operating Environment Filter on microcontrollers that require the Normal Operating Environment filter may prevent the microcontroller from coming out of reset.

MC68HC16P3
Normal
High Stability

MC68HC916P1
Normal
High Stability

MC68HC916R1
Normal G72C
High Stability None

MC68HC16R3
Normal H34K
High Stability

MC68HC916R3
Normal H70E
High Stability

MC68HC16V1
Normal E47W, F33P, G87B
High Stability

MC68HC916X1
Normal
High Stability H97A

MC68HC16Y1
Normal D34F, D16P, D38W, D57W, E72G, F94CMC68HC916Y1
Normal E41C
High Stability

MC68HC916Y2
Normal E83M
High Stability

MC68HC16Y3
Normal F83C
High Stability None

MC68HC916Y3
Normal G45B, F43K
High Stability

MC68HC916Y5
Normal
High Stability

MC68HC16Z3
Normal G26C
High Stability H32H

MC68HC16S2
Normal G12C
High Stability None

MC68CKZ1
Normal H29C, H69J
High Stability

MC68CMZ1
Normal H29C, H69J
High Stability

MC68HC16Z1
Normal H29C, H69J, D35C, D12N, E45F, E62W, E69W, E54F, F73T, F67V,
High Stability

MC68HC16Z2
Normal D55T, E34C, E11P, G11D
High Stability

MC68HC16Z4
Normal H63H
High Stability H93K
MC68331
Normal C47T, E93N, E95B, F43E, G91H, H17A
High Stability

MC68332
Normal B30G, C81F, C32J, C17P, C53T, D88A, D33F, D87M, E38R, F78A, F98R, G10K, G30S
High Stability J66A, J30C

MC68F333
Normal C37T, D59N, E66B, F48H, F34W, G50G
High Stability G21R,

MC68334
Normal D79M,
High Stability E45M, F44N, G38F

MC68335
Normal E97F, F60G, G88E
High Stability H12J

MC68336
Normal D36J, D65J
High Stability F60K, F70K

MC68338
Normal F84R, G44C, G86F, G88T, H99D, H17D, G88T, H17DMC68339
Normal F63B, F68G, G70J, H57P
High Stability

MC68376
Normal
High Stability F66K, F71K

The general cause of this problem is that the VCO is operating at a frequency that is out of spec. The maximum frequency for the VCO is two times the maximum rated frequency of the device. That is, a 16.7 MHz part would have a maximum VCO frequency of 33.4 MHz, a 20.9 MHz device would have a maximum VCO frequency of 41.8 MHz and so on.

When a modular device first powers up, the VCO will be operating at 4 times the system clock frequency. Thus, if the device has a system clock of 8.38 MHz the VC0 frequency is 33.52 MHz which is within the electrical specifications of the part.

If an attempt is made to run a device rated at 16 MHz with a system clock speed greater than 8 MHz, the Clock Synthesizer Control Register must be properly programmed such that the maximum VCO speed is not exceeded.

To do this, the "X" bit in the SYNCR register must be set to a logic 1. This bit controls a divide by 2 circuit which sits between the output of the VCO and the Intermodule Bus Clock line. This divide by 2 circuit does not sit inside the feedback path of the PLL/VCO. By setting the X bit to a logic 1, the divide by 2 circuit is bypassed which will cause the VCO frequency to only be two times the system clock speed instead of the 4 times speed. With the X bit set to a logic 1, a system clock speed of 16.7 MHz can be obtained while running the PLL/VCO at 33.52 MHz which is within the electrical specifications.

Yes. The TPU parameter RAM is composed of 16-bit words. The TPU Parameter RAM can be read as bytes. However, writing the TPU Parameter RAM as bytes can cause problems. If the lower byte of a TPU Parameter RAM location is written with a "byte wide" access, the upper byte of the TPU Parameter RAM location will be written to $FF. Depending upon how the TPU Parameter RAM is used, this particular feature may or may not cause a problem with the system software.

However, it is highly recommended that all accesses to the TPU Parameter RAM be word wide accesses on word boundaries to prevent any possible corruption of the RAM.

No. In general, grounding the DSACK lines to give either an 8-bit DSACK or 16-bit DSACK will cause an external memory cycle to take three clock cycles. In some board level designs the system designer depends upon all external memory accesses to be exactly three clock cycles. By assuming that all external memory accesses are three cycles, the board designer can incorrectly design a board such that two three-clock cycle accesses could be run back to back.

In the CPU32 design, a normal three-cycle bus access can be extended by one clock cycle when an op code prefetch occurs on the first cycle of an Interrupt Acknowledgement Cycle.

This extra cycle will generally have no affect that can be detected by the user or the system hardware or software. However, in the case where the board designer was depending upon back to back three cycle memory accesses, memory corruption can occur because a memory cycle took an extra cycle.

To compensate for the problem of an extra clock cycle on certain external bus cycles, any external memory controllers should wait for the de-assertion of either Data Strobe or Address Strobe before allowing the next memory cycle to begin.

Conclusion: When designing an external memory controller, make sure that the current memory cycle has completed by observing the de-assertion of AS or DS before starting the next memory cycle.

One cause for the external bus to stop running bus cycles is that the Bus Grant Acknowledge has floated or been driven low. The Single Chip Integration Module (SCIM) can operate in the Single Chip, 8-Bit Expanded and 16-Bit Expanded Bus Mode. In the Single Chip and 8-Bit Expanded modes, the Bus Grant Acknowledge pin always performs the BGA function at the release of reset. In the 16-Bit Expanded Mode, the Bus Grant Acknowledge pin will perform the BGA function if Data Bus 10 is high at the release of Reset. If the BGA pin is either pulled low or floats low, the external but will halt immediately.

To prevent the errant condition from occurring, a pull up resistor must be used to pull the BGA pin to a logic 1. This problem is temperature dependent. Also, if BGA is floating, capacitive coupling between the BGA pin and another board trace can cause the BGA pin to float low. This problem can appear to be software related as the software can cause certain "patterns" to be driven on the address and data busses that will be more prone to pull floating pins one way or another. However, any connection between the BGA pin floating to a logic 0 and the software that is running is simply coincidental.

Always put a pull up resistor on the BGA pin.

No. The SPIF bit indicates that the last byte in the QSPI transmit RAM has been loaded into the QSPI shifter. The setting of the SPIF bit indicates to the CPU that new data can be written to the QSPI transmit RAM

In some cases, programmers have cleared the SPE bit with their software as soon as the SPIF bit sets. This will truncate the last transmission of the QSPI.

The proper method to disable the QSPI is to monitor the SPE bit. This bit will automatically clear itself. When this bit clears, the current transmission plus a programmable delay time will be finished and there will not be a problem with changing the function of the QSPI or starting another transmission.

Once again, the QSPI will be active until the SPE bit self clears. No attempt should be made to reprogram the QSPI registers or transmit / receive RAM until the SPE bit self clears.

Mbug resides in ROM on the MCORE microcontroller. Picobug resides in the flash memory on the EVB1200 and CMB1200. With jumper W9 removed, the microcontroller will start executing Mbug from the microcontroller's internal ROM after a hardware reset. With jumper W9 installed, the microcontroller will start executing Picobug after a hardware reset.

The following figure shows the supply voltage ranges required to operate these microcontrollers. To ensure correct microcontroller operation, V_DD_IO should be greater than or equal to V_DD_CORE and V_DD_OSC during a power-up interval.

No. For a pin to be under the control of the QSPI, two conditions must be met. The first condition is that the selected QSPI pins must be assigned to the QSPI using the QPAR register. The second condition is that the QSPI is enabled, that is, the SPE bit in QSPI Control Register 1 is set to a logic 1.

To send a transmission using the QSPI, the transmit RAM is loaded with the data to be transmitted. Then, the SPE bit is set which enables the QSPI. As soon as the SPE bit is set all pins that are assigned to the QSPI via the QPAR register will be under the control of the QSPI. At the end of the transmission, the SPE bit will automatically clear itself. When the SPE bit becomes a logic 0, all of the QSPI pins will revert to the control of the Port QS Data Register and the Port QS Data Direction Register.

A consequence of the control of the QSPI pins switching between the QSPI and the Port QS Data and Data Direction Registers is that "false" transitions can be created on the QSPI clock line. Take an example where the inactive level of the QSPI clock is low. If bit 2 of the Port QS Data Register is a logic 1 and the Port QS Data Direction Register has made the QSPI Clock Pin, SCK, into an output, the SCK pin will output a logic 1. As soon as the SPE bit is set, the SCK pin will switch to the control of the QSPI. As our example calls for the resting level of the clock to be a logic 0, the SCK line will take a logic 1 to logic 0 transition when the SPE bit is set. To all of the SPI devices connected to the QSPI, it will appear as though they have just received a valid clock edge which is not the case. The peripherals will have received an "unintended" transition. When the QSPI disables itself by clearing the SPE bit, a second "unintended" transition will occur. This, of course, will totally unsynchronize QSPI transmissions. The solution to this problem is to make sure that the Port QS Data Register is properly programmed to prevent these "unintended" transitions. In the present case, the data register bit for SCK should always be the same as the resting or inactive level of the SCK line.

No, the address lines cannot be set to go into a high impedance state. And, driving the microcontroller's address, data, and control lines with another bus master could possibly damage the microcontroller. To in-circuit program a memory device, the address, data, and control lines of the microcontroller could be isolated from the other bus master with external logic. Also, the microcontroller could be commanded through its OnCE debug port to perform the programming operation. Motorola offers an enhanced background debug interface (EBDI), that, used with a personal computer and an appropriate software utility, will control the microcontroller through its OnCE port. With an EBDI, the microcontroller could be commanded to program a non-volatile memory device.

No, the address lines cannot be set to go into a high impedance state. And, driving the microcontroller's address, data, and control lines with another bus master could possibly damage the microcontroller. To in-circuit program a memory device, the address, data, and control lines of the microcontroller could be isolated from the other bus master with external logic. Also, the microcontroller could be commanded through its OnCE debug port to perform the programming operation. Motorola offers an enhanced background debug interface (EBDI), that, used with a personal computer and an appropriate software utility, will control the microcontroller through its OnCE port. With an EBDI, the microcontroller could be commanded to program a non-volatile memory device.

Yes, a 32.768 kHz crystal oscillator must be connected to pins EXOSC and XOSC. The oscillator is required in order for the microcontroller to come out of a hardware reset. After power is applied to the microcontroller's V_BATT pin, approximately one second (2¹⁵ + 8) 32.768 kHz clock cycles must occur before the microcontroller will be allowed to exit the reset state.

Additionally, a supply voltage, VCCI, must be applied to pin X V_DD in order to power the 32.768 kHz oscillator. Please refer to the following figure:

Presently, no. A CLKIN frequency of 32 MHz corresponds to a cycle period of 31.25 ns. According to specification, CS# can be asserted up to 29 ns into the first clock cycle leaving only 2.25 ns in that cycle for accessing SRAM and for propagation delay from any external logic in series with the CS# signal. At least one wait state should be selected using the chip select configuration register for the chip select concerned.

A sector of flash memory that the new firmware must be written to was inadvertently write-protected when the EBDIs were manufactured. The sector cannot have the write-protection removed without applying a voltage on one of the pins of the flash memory chip. Please contact Global Data Specialist, 3707 E. Broadway, Phoenix, AZ 85040, (602) 437-4331, for repair or replacement of an affected EBDI. An EBDI connects to an MCORE MCUs OnCE (on-chip emulation) port to

Yes, a power source must be connected to V_BATT whether or not the microcontroller will be battery backed up. V_BATT must be at a voltage greater than or equal to 1.8 V and less than or equal to 3.6 V. V_BATT can be connected to the V_CCE power source (V_CCE supply). Please refer to the following figure:

No. Here is an example where internal RAM/ROM accesses will not be visible on the external bus. If the show enable (SHEN) bits in the external interface module configuration register (EIMCR) are set to 01, show cycles enabled, and the chip select assert (CSA) bit in the pertinent chip select configuration register is set to 1, an idle cycle will be inserted between back-to-back external accesses. Internal RAM/ROM accesses can occur during this idle cycle, but will not be seen on the external bus.

In-circuit programming of the 68HC908GP32 using the PROG08 module of the ICSGP software is done using the following steps. The PROG08 software supports monitor mode communication only. Therefore, the device must be in monitor mode. See the Monitor ROM section of the 68HC908GP32 data book for a description of monitor mode entry requirements. Also, proper clocking of the device must be provided to facilitate an acceptable communication rate. The table labeled 'Monitor Mode Signal Requirements and Options' in the Monitor ROM section specifies under what conditions one can acquire 9600 baud communication.

1. Bring up the IDE of the 32-bit version of the ICS software.
2. If the program has not been assembled, then select the .ASM file from the File menu.
3. Click assemble/compile icon in the tool tray. Results of this operation are shown at the bottom of the window. If unsuccessful, then debug program and try to assemble again.
4. Connect to the target through an available com port. Connection to PTA0 on the target must be through a level translator.
5. Click the Programmer (EXE2) icon.
6. If 'Can't Contact Board' message box comes up, then select the correct com port that connects to the target, select the correct baud rate as determined by the internal frequency of the target micro (baud = F_BUS/256), and uncheck the checkbox labeled 'Serial Port DTR controls target power. Click on the 'Retry' button.
7. Turn MCU power off and then on when instructed to do so.
8. If 'Contact with 68HC08 Monitor established' message is shown in the Status window, then a message box will be shown asking which programming algorithm to use. Select '908_gp32.08p' and click on 'Open' button. A message is shown in the Status window saying 'Loading programming algorithm ... Done.' If PROG08SW fails to establish contact with the target micro, then there is something wrong with one or more settings. Check to make sure that:
   • The baud rate selected matches F_BUS/256 in the target micro. Note that the PLL will only be initiated when V_SS is applied to IRQ on a blank part. Otherwise, F_BUS = F_OSC/4 if PTC3 is high or F_BUS = F_OSC/2 if PTC3 is low.
   • V_TST is at the specified level and is applied to IRQ (if part is not blank).
   • Port C pin requirements are met (if part is not blank).
   • The correct com channel has been selected.
   • Communication from the PC to PTA0 is through a level translator and a tri-state buffer in the same circuit as, or similar circuit to, the Monitor Mode Circuit in the data manual. PTA0 needs a pull up of about 10 kohms.
   • PTA7 is grounded.
   • A power-on reset, not a RST pin reset, is performed when requested.

   Note: The 68HC908GP20 and 68HC908GP32 contain a security feature based on information that the user programs to the part. Security bytes are specified in addresses $FFF6 - $FFFD. The PROG08SW software continually records any changes to these security bytes and stores them in the file SECURITY.INI. The information in this file is also shared with P&E's In-Circuit Debugger and In-Circuit Simulator Software. This allows the user to reset the device and still have access to the monitor mode. The PROG08SW software automatically will attempt to access the part by trying the default (nothing written) and up to the last 10 sequences of bytes that have been written to the part. If, after trying each of the sequences of bytes stored in the SECURITY.INI file, the PROG08SW software is unable to access the part, a security dialog box will be displayed which allows the user to specify either the value of these eight bytes or the s record file with which the device is currently programmed.

9. Double click 'SS Specify S record' in the 'Choose Programming Function' window. A message box will come up allowing the selection of the s-record file to be used to program the device. Select the file and click on 'Open' button.
10. Double click 'BM Blank check module' in the 'Choose Programming Function' window. 'Erased' message will be displayed in the Status window if the part is erased. If the part is not erased and it should be, then double click 'EM Erase Module' in the 'Choose Programming Function' window. 'Erased' message will be displayed in the Status window.
11. Select 'PM Program Module' to program the device with the selected S record file. 'Programming Address $xxxx. Done.' Appears in the Status window.
12. Verify, uploading, or other functions can now be performed in a similar manner.

For a description of how one can prepare a device for re-programming, please see AN-HK-32 -- In-Circuit Programming of FLASH Memory in the MC68HC908GP32. Also see AN-1770 -- In-Circuit Programming of FLASH Memory in the MC68HC908GP20 - for a general discussion of monitor mode entry and FLASH programming.

1. The amount of FLASH in the 68HC908GP32 is 32K bytes while the JL3 contains 4096 bytes of FLASH.
2. The technology of the FLASH in these two devices is the same and is thus programmed the same. However, the program page size of the 68HC908GP32 is 128 bytes while the page size of the JL3 is 32 bytes. The 68HC908GP32 can be erased in blocks of 128 bytes while the JL3 is erase in blocks of 64 bytes.
3. Block protection ranges are also different. In the 68HC908GP32, there are 256 block sizes that can be protected. The size of each of these blocks is a multiple of 128 bytes where the upper end of the protected range is always $FFFF, such that the smallest range protected is $FF80-$FFFF (128*1) and the largest range protected is $8000-$FFFF (128*256). In the JL3, there are 64 block sizes that can be protected. The size of each of these blocks is a multiple of 64 bytes where the upper end of the protected range is always $FFFF, such that the smallest range protected is $FFC0-$FFFF (64*1) and the largest range protected is $EC00-$FFFF (64*64).

Using an external capacitor of 10 pF, with V_DD = 5.0 V, and operating at room temperature, the RC characteristics of the 68HRC908JL3 are approximately as follows. These values for resulting oscillator frequency are approximate and will vary from part to part. Please consult the data manual for more accurate and/or up-to-date data. Internal frequency will be F_OSC/4.

Resistance/Ohm	FOSC (MHz)
5000	14
5600	13
6200	12
6800	11
7500	10
8200	9
10000	8
12000	7
15000	6
18000	5
20000	4.5
26000	3.5
30000	3.0
39000	2.5
47000	2
56000	1.75
62000	1.5
67000	1.4
70000	1.35
75000	1.25
82000	1.15

Programming the 68HC908GP32 can be done at V_DD= 5 V or 3 V (+/-10%). If programming in monitor mode and the reset vector is not blank, then a V_TST of V_DD + 2.5 V to 9 V must be applied to IRQ. Note that V_TST does not supply current, it is only a signal that, when present, allows entry into monitor mode. Monitor mode programming is required to disable write protection and is normally not used in circuit. Any block in the 68HC908GP32's FLASH can be write protected in user mode without high voltage. The higher voltage provides an additional precaution to avoiding unintentional write/erase since the write protection cannot be disabled in user mode.

Estimated program time is about 30 uS per byte, or 1 second for the entire 32 K array. This time does not include verification or communication time, which is the bottleneck unless communicating at, or faster than, 115.2 kbaud.

The 68HC908GP32 is specified for 10,000 write/erase cycles over the full operating temperature range of -40 to +85 centigrade.

Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control.

Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control.

These two devices are intended to be 100% compatible in all regards, except for the size and type of FLASH on board. They have the same modules, the same amount of RAM, same register structure and same pinout and package types. There will be slight variations in current draw, and the user should consult the electrical specifications in the user's manual for the exact range of values.

1. The amount of FLASH in the 68HC908GP20 is 20 K bytes, the 68HC908GP32 contains 32 K bytes.
2. The FLASH in the 68HC908GP32 can be programmed much faster than the FLASH in the 68HC908GP20. Typically this difference is at least 25:1, as the 68HC908GP32's FLASH takes about 30 uS per byte while the 68HC908GP20's FLASH can take anywhere from 1 to 50 mS per 8-byte page.
3. Since the FLASH technology is different in these two parts, the programming algorithm and the program control registers are different. The 68HC908GP20 uses a "bump program/margin read" algorithm while the 68HC908GP32 can be programmed reliably in one pass and does not require (or support) a margin or hard read.
4. The program page size of the 68HC908GP20 is eight bytes while the page size of the 68HC908GP32 is 128 bytes. When programming the 68HC908GP20 one must program all bytes in a page at a time, whereas the 68HC908GP32 has no such restriction. One can program a partial page with no implication as to affecting the endurance of the part.
5. The selectable erase sizes for these two parts are different. The 68HC908GP20 can be erased in blocks of 64 bytes, 512 bytes, 4K bytes, 16K bytes or the full array. The 68HC908GP32 can be erased in blocks of 128 bytes or the full array.
6. An erased cell in the 68HC908GP20 reads as $00 while an erased cell in the 68HC908GP32 reads as $FF.
7. Block protection ranges are also different. In the 68HC908GP20, either the block from $C000-$FFFF or the entire array ($B000-$FFFF) can be protected. In the 68HC908GP32, there are 256 block sizes that can be protected. The size of each of these blocks is a multiple of 128 bytes where the upper end of the protected range is always $FFFF, such that the smallest range protected is $FF80-$FFFF (128*1) and the largest range protected is $8000-$FFFF (128*256).
8. While programming and erasing can take place at 3 V or 5 V for both devices, the 68HC908GP20 must be programmed/erased at 2 MHz or greater while the 68HC908GP32's FLASH can be modified at 1 MHz or greater.
9. Endurance for these two devices differ greatly. While the 68HC908GP20 has an endurance specification of 100 write/erase cycles, each byte of the 68HC908GP32 can be written and erased up to 10,000 times across the rated temperature range.

Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control.

Yes, you can use the output compare interrupt in the 68HC08 without placing the associated pin under timer control. Do so by clearing the ELSxB and ELSxA bits. This places the timer pin under port control.

The port pins that share functionality with the SPI on the 68HC705C8A are unidirectional, but on the 68HC705C9A they are bidirectional. To use the 68HC705C9A SPI, you must configure the appropriate data direction register bits for that port according to the direction of data flow. Set the DDR bit as an input for the SPI input pin and as an output for the SPI output pin.

Many Motorola MCUs provide an option for RC clocking that requires no external components or just an external resistor to provide clocking for the MCU. This provides a clock source with a very wide accuracy tolerance. The generated frequency from the same external components can vary in the same MCU from lot to lot, due to process variations.

IMPORTANT: If your application relies on an accurate clock source frequency, DO NOT use the RC oscillator as a clock source.

The oscillator frequency is very sensitive to capacitive loading. Any change in design, especially due to board lay out, device sockets, or conformal coating, can drastically change the resulting RC oscillator frequency.

In cases where wide frequency swings cannot be tolerated, an external clock source should be used.

Always note that a canned oscillator is always best when dealing with EMC issues. In the event that a canned oscillator is not an option the following should help to reduce the amount of noise emulating from the circuit.

1. Protect OSC1 and OSC2 from all sources of noise. This can be done by locating the crystal and all related external components as close to the IC as possible.
2. Ensure that the ground connection for capacitors are using a single node.
3. Ensure that V_SS has no current going through it.
4. Tie grounds directly, while ensuring that they go to the correct V_SS (ie V_SS vs B_SSA)

Buffered inverters should not be used for crystal oscillator designs. They usually have a gain greater than 100. With a higher gain, one might see a spur, harmonic, or overtone caused by the part running at the wrong frequency or between frequencies. Buffered gates, however, can offer some advantages. High gain will result in a very fast internal transition time, causing a reduction in the amount of operating current.

S-RECORD FORMAT DESCRIPTION
The S-Record format for output modules was devised for the purpose of encoding programs or data files in a printable format for transportation between computer systems.

S-RECORD CONTENT
When viewed by the user, S-Records are essentially character strings made of several fields that identify the record type, record length, memory address, code/data, and checksum. Each byte of binary data is encoded as a 2-character hexadecimal number: the first character represents the high-order 4 bits, and the second represents the low-order 4 bits of the byte.

The 5 fields that comprise an S-Record are shown below:

TYPE

RECORD

LENGTH

ADDRESS

CODE, DATA

CHECKSUM

The S-Record fields are composed as follows:

Field	Printable Characters	Contents
Type	2	S-Record type - S0, S1, etc.
Record Length	2	The count of the character pairs in the record, excluding the type and record length.
Address	4, 6, or 8	The 2-, 3-, or 4 byte address at which the data field is to be loaded into memory.
Code, Data	0 - 2n	From 0 to n bytes of executable code, memory-loadable data, or descriptive information. For compatibility with teletypewriters, some programs may limit the number of bytes to as few as 28 (56 printable characters in the S-Record).
Checksum	2	The least-significant byte of the one's complement of the sum of the values represented by the pairs of characters making up the record length, address, and the code/data fields.

Each record may be terminated with a CR/LF/NULL. Additionally, an S-Record may have an initial field to accommodate other data such as line numbers generated by some time-sharing systems. Accuracy of transmission is ensured by the record length (byte count) and checksum fields.

S-RECORD TYPES
Eight types of S-Records have been defined to accommodate the several needs of the encoding, transportation, and decoding functions. The various Motorola upload, download, and other record transportation control programs, as well as cross assemblers, linkers, and other file-creating or debugging programs, utilize only those S-Records that serve the purpose of the program. For specific information on which S-Records are supported by a particular program, the user manual for that program must be consulted.

The important S-record types for 8-bit MCUs are:

S0: The header record for each block of S-Records. The code/data field may contain any descriptive information identifying the following block of S-Records. The address field is normally zeroes.

S1: A record containing code/data and the 2-byte address at which the code/data is to reside

S9: The termination record for a block of S1 records. Address field may optionally contain the 2-byte address of the instruction to which control is to be passed. If not specified, the first entry point specification encountered in the object module input is used. There is no code/data field.

Only one termination record is used for each block of S-Records. Normally, only one header record is used, although it is possible for multiple header records to occur.

Because a Motorola microcontroller and the PC UART work with different voltages, a level translator IC is necessary. A common IC used for this function is the MC145407, which is capable of producing RS-232 voltages from a single 5 V supply. An example circuit is shown here.

Some applications have a suitable clock provided that could be used in place of an external crystal or ceramic resonator. Using an external clock into the OSC1 (input) pin of the oscillator may not be sufficient to drive the MCU. The gain of the internal oscillator inverter of most new 68HC05s is very low (a gain of 3 to 5 is common) as this prevents the crystal from being overdriven and creating excessive EMI.

It is recommended that the oscillator be driven with an additional inverted signal into OSC2. This simulates the action of the crystal and drives the oscillator properly. An advantage of this is often improved EMS performance (immunity to noise) where the clock has fast edges and does not allow injection of noise spikes into the oscillator circuit of the MCU.

• Whenever possible, use a multi-layer board with a separate ground plane.
• Place the crystal and all other associated components as close to the osc1 and osc2 (oscillator pins) as possible.
• Do not run a high frequency trace under either Rf or Rs.
• Ensure that the ground for the bypass capacitors is connected to a solid ground trace.
• Do not run high frequency conductors near the oscillator, Rf, or Rs.
• Tie the ground trace to the ground pin nearest osc1 and osc2 (oscillator pins). This prevents large loop currents in the vicinity of the crystal.
• Tie the ground pin to the most solid ground in the system.
• Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable.

A canned resonator is a single package that includes the oscillator and all required external components. The canned resonator can be used to help provide noise immunity. The package for a canned resonator is electrically shielded. Its rise and fall time is much faster than a crystals. With less transition time, there is a smaller chance of pulses occurring.

Crystal power dissipation can cause unstable operation by overdriving the crystal. If not accounted for it may even cause the quartz to actually break in extreme cases. Listed below are some steps that may be used to limit crystal power dissipation.

1. Reduce the amplifier gain by decreasing the size of the bias resistor Rf. Note that this will increase I_DD.
2. Reduce the amplifier gain by decreasing the size of the bias resistor Rf. Note that this will increase I_DD.
3. Reduce the input voltage to the crystal by increasing the corner frequency for the R/C low pass filter. Note that this may cause the start-up time to be increased.
4. Lower the load capacitance.
5. Reduce the power supply voltage.
6. Use a resistive voltage divider to reduce the output of the amplifier.
7. Add a resistor to the input of the amplifier.

There are three questions one should consider when discussing series vs parallel crystal oscillator circuits.

1. What is the mode of the resonance within the crystal?
2. Is the crystal operating at the frequency of its lowest impedance or its highest impedance?
3. What external influences does the circuit introduce?

In parallel circuits, such as the pierce, the crystal resonates with external capacitors and thus the crystal operates between the lowest impedance frequency and highest impedance frequency, where the impedance is inductive. This means that the operating frequency will be just above the lowest impedance frequency. When the load capacitor is placed in series with the resonator, the low impedance frequency is shifted up. Effective resistance at the new resonance frequency is higher than that of the resonator alone. This resistance is referred to as ESR. When the load capacitor is placed in parallel with the resonator, the anti-resonant frequency is shifted down. The resistance at this frequency is referred to as EPR. Note that ESR and EPR are equal.

Series load capacitance is used to measure the resonator's operating frequency. This is because the lower impedance is easier to measure. Parallel load capacitance, however, is most frequently used.

Crystal drive level is the power it takes to drive the crystal. It is important in that it directly relates to power dissipation of a crystal (refer to faq on how to reduce crystal power dissipation).

For a Pierce Circuit and a circuit with a load capacitance in series with a crystal, the following equation may be used.

P = 2 x R1 x [PI x F x (CL+CO) x V]

Where:

CL = Load capacitance
CO = Shunt capacitance (and the sum of the electrode capacitance of the crystal and package capacitance)
F = Frequency
IC = RMS current through the crystal
P = Power
PI = 3.14...
R1 = Crystal resistance
V = V_OLtage across the crystal

At 4 MHz, when all control bits are cleared on the BAUD rate register, the maximum transfer rate is 230,000.

A microcontroller is a highly sensitive state table. At reset it expects a set of signal conditions as an input to get into the correct mode of execution. These conditions, MODA and MODB, are set during RESET. If the timing on these conditions is not met properly because of random spikes either below or above the rails the following symptoms will be experienced when running your application:

1. EEPROM corruption either bit or byte.
2. Incorrect execution of the program.
3. I/O pins will not read the proper expected conditions.

Yes, an article has been written that illustrates how to implement IIC with an SPI device. The article can found in EDN February 18, 1988, and the article Serial techniques expand your options for uC peripherals was written by Naji Naufel.

Mode 0

• Manually controlled by software
• Intended for simple analog readings, particularly 8-bits or less
• Minimal software overhead
• Can be operated as in-line background code
• Can be an interrupt driven timing task in the foreground
• Avoid interrupts during software timing loops
• Timing methods:
• Software loops
• Reads of TOF in 16-bit Timer (but not automatic like modes 2 or 3)
• Reads free-running core timer
• Setup is ATD1 = ATD2 = 0

Mode 1
 

• Semi-manually controlled by software (discharge cycle begins automatically when CPF2 is set)
• Can be operated like Mode 0
• Be sure to manually reset CHG bit if time lasts too long

Mode 2
 

• Automatic mode which runs continuously while being driven by 16-bit timer
• Intended for slower sampling of high precision reading where the timer ICF captures the time from the last TOF
• TOF and ICF flags continue to control ramp capacitor even if 16-bit timer interrupts are disabled
• Be sure to match up ICF with proper TOF
• Can be operated as background code with some attention flags
• Most likely will be an interrupt driven timing task in the foreground
• Timing method:
• 16-bit timer, 8 f_OSC cycles/count
• Setup is ATD1 = 0, ATD2 = 1

NOTE: Be sure to clear TOF before clearing ICF and always set the IEDG bit in TCR = 1

Mode 2 also allows for overtime testing using OCF to halt bad conversions sooner and make next TOF ready to start new conversions.

Mode 3
 

• Automatic mode runs continuously and is driven by the 16-bit timer
• Intended for faster sampling of high precision readings where the timer ICF captures the time from the last OCF
• OCF and ICF flags continue to control ramp capacitor even if 16-bit timer interrupts are disabled
• Be sure to match up ICF with proper OCF
• Can be operated as background code with some attention to flags
• Most likely will be an interrupt driven timing task in the foreground
• Timing method:
• 16-bit timer, 8 f_OSC cycles/count
• Setup is ATD1 = 1, ATD2 = 1

NOTE: Be sure to clear OCF before clearing ICF and always set the IEDG bit in TCR = 1.

Mode 3 cannot perform overtime test using OCF to halt bad conversions sooner. So a bad conversion will use the next OCF for a time limit, while the old conversion time is replaced.

Symptom:
The MDLC module is capable of receiving messages successfully only when the bit timing is equal to or greater than the minimum values plus 5% of the nominal values, as published in the 68HC705V8 Specification Rev. 2.1. (Section 17.11.7)

Explanation:
Most customer run J1850 communications at nominal timing values and will never see this problem, however, it does exist (in the devices tested) and needs to be addressed.

Solution:
Simply increase the bit timing to above the threshold of minimum plus 5% nominal values. This should prevent any problems related to this bug.

The CONFIG register can be programmed with the SPGMR11 under PROG11, or one can build a circuit placing the 68HC11 in bootstrap mode and using PCBUG11 to program the CONFIG register. One can find the circuit for bootstrap mode in appendix A of the PCBUG11 Manual or construct a circuit where MODA and MODB are tied to ground and IRQ, XIRQ, and RESET are pulled up through a 4.7K Ohm resistor. Transmit and Receive on the MCU must go through an RS232 Level shifter. The part number for socket E56, the Motorola level shifter, is MC145407. Please refer to the data sheet for more information. With PCBUG11 and Bootstrap mode on the 68HC11, getting to know the part is easy and inexpensive.

For the NOSEC bit to work on the 68HC11 Family of microcontrollers, the nomenclature on the micro must specify that the feature has been enabled. This option does not come enabled on all members of the family-

1. Make sure the V_DD, MODA, and MODB have achieved their proper logical levels at the time the microcontroller releases RESET. The processor will release reset after seeing 4064 E clock cycles. Should the processor release RESET before these signals are stable the micro will not RESET as desired. For timing specifications please refer to M68HC11RM/D. There is one parameter not defined that is the time for Reset to transition from low to high.
2. Make sure that your PCB lay out allows configuration of MODA and MODB.
3. Make sure that RESET has a 4.7k Ohms pullup and that no capacitance is used between RESET and the ground plane.

Guaranteed to 10000 writes across rated temperature range (not just room temperature) and 10 years data retention.

The typical time for a bulk erase is 10 ms.

The biggest enemy of an EEPROM cell is the introduction of a transient that violates the electrical specification of the microcontroller. A transient in the negative domain can cause damage to the cell to the point of rendering the cell useless.

NO. Motorola discourages customers from using mode. If you purchase a programmer, you should find out if the programmer uses the bootstrap mode to program the microcontrollers.

In an OTP device, the part does not have a window with which to erase the EPROM array. This prevents data loss due to UV light exposure. In a windowed part, you should always cover the window with a label or piece of tape (anti-static tape!) to prevent UV light from erasing the EPROM.

Unfortunately, heavy switching will affect the voltage reference applied to the ADC, and accuracy and precision of the ADC module are a function of the reference voltage. Proper decoupling is recommended.

Users can find the algorithms listed in the technical data for the series in use.

If it is a windowed device, one can expose the device to UV for about 30 minutes or so to erase the memory. On an OTP (one time programmable) part, data is retained for many years and cannot be erased with UV light (no window!).

1. Improve supply line decoupling to eliminate any high frequency noise which may be coming out of the microcontroller. The recommended decoupling capacitor size for single- chip applications is 0.1 microfarads.
2. Printed Circuit Board lay out is important. For ADC input lines that are placed close to digital lines, noise is coupled inducing ADC errors, therefore, it is recommended to route ADC lines and Digital lines a part from each other.
3. Avoid operating the ADC in the internal RC clock mode if possible, especially in expanded mode. In RC clock mode, the ADC is running asynchronously to the rest of the processor, eventually causing sensitivity window to overlap a period of bus activity noise.
4. For best results, run the microcontroller in single-chip mode.

The highest susceptibility of the converter to supply noise occurs in the last 30 nanoseconds (approximately) in the sample period (6 microseconds) of a conversion, which takes 16 microseconds at a 2.1 MHz bus frequency. Any disturbance to the ADC during this 30 nanosecond window is capable of causing an error. The most common source that disturbs the ADC are: supply noise generated internally by output buffers switching capacitive loads, especially in expanded/multiplexed operating mode. Decoupling for expanded mode is recommended and a capacitance should be applied at 1 uF paralleled with .01 uf. In single mode 0.1 uF is sufficient.

An analog-to-digital converter is a device used to read a voltage from an infinitely variable (analog) voltage source and convert that voltage to the closest digital equivalent. An 8-bit ADC, such as those found in the 68HC11 Family, can convert an analog voltage to any one of 2⁸ (256) discrete digital values.

In the 68HC11 Family of microcontrollers, precision is:

(V_OLtage reference high) - (V_OLtage reference low)/ V_DD

1/-1LSB @ 2MHz

This assumes that V_DD is 5 V. 1 LSB would be measured as 1/256v * Full-scale voltage reading (ideally, 5 V), which would be 0.01953 V (19.5 mV).

If you compute:

SCIbaud = XTAL / 2 * 16 * BR

where BR = 1 and Eclock = 4MHz.

This gives a maximum transfer rate of 500 K.

A level shifter commonly used in development tools is the MC145407P.

Typically, the 68HC11 Family has one SPI port.

Typically, the 68HC11 Family has two modes with a the capability to change clock polarity.

The typical circuit can found on the M68HC11PCBUG11 User's Manual, M68PCBUG11/D in appendix A. However, to setup up the part in its simplest form, MODA/B are tied to ground and IRQ and XIRQ are pulled up through a 4.7 kOhm resistors.

By enabling an Output Compare and each time the program executes the interrupt handler and offset value is added to TCNT and stored to the respective TOCX.

No.

• BDM Lockout feature implemented. Writing a bit of a shadow register of EEPROM will disable the Background Debug Mode at the next reset. Writing or erasing the shadow bit is
• In PLL module, the reference of XFC is modified from V_SSPLL to V_DDPLL. For better noise immunity and minimizing the jitter it is recommended to connect the loop filter of the PLL to V_DDPLL instead of V_SSPLL.
• MI-Bus interface implemented in one of the on-chip SCI's.
• New clock chain. As BDM clock comes directly from the oscillator, it will functions nor-mally even if the bus frequency is changed by the software (see the figure).
• The output of Slow Divider (SLWCLK) can be output to port PE7 by enabling the CALE bit in PEAR register ($000A). The specification will be the same as on MC68HC912DA128/ DG128.
• The slow divider ratio more flexible. The ratios are 2, 4, 8, 12, 16, ..., 252 by steps of 4.
• New PWM module. Please refer to the PWM specification. The difference between MC68HC912DA/DG128 and MC68HC912D60 is the PORT P which has four I/O ports PP[7:4] implemented on D60.
• More power savings in RAM and BDM modules in wait mode.
• The output buffers drive on all ports reduced by 25% in order to reduce susceptibility to ringing.
• The PE1 (IRQ) pull up is now selectable with PUPE bit of PUCR register, same as the PE0 (XIRQ) pin. The pull up is enabled at reset.

The biggest enemy of an EEPROM cell is the introduction of a voltage transient that violates the electrical specification of the microcontroller. A transient in the negative domain can cause damage to the cell to the point of rendering the cell useless.

If any application generates a glitch into the bus and it is interpreted a short within the Start Of Frame by the BDLC can cause the BDLC to generate a pulse train. The fix is to include the following piece of code on invalid_handler.

serve7:

inc	inv_int
clr	status
bset	bcr2,y,$20	; Setting 4X mode.
bset	portp,y,$20	;Set PP5 for delay characterization
jsr	Delay	;Delay 50 to 60 uSec.
bclr	portp,y,$20	; clear PP5
bclr	bcr2,y,$20	;Clear the 4X mode
rti

In older mask sets, like 1H91F, writes to the BDR must be within 370 us or the BDLC state machine will generate an Invalid Symbol. The state machine on the 9H91F should change this condition to not care about the time delay between bytes.

Your program should have an executive responsible for updating the transmit buffer. After the buffer is filled, it is useful to send the first byte and the BDLC will generate the correct sequence of interrupts with BSVR values set to TDRE. This sequence will send the entire buffer provided that the tdre_handler is designed to write all the bytes to the BDR.

Yes, the BDLC generates an interrupt. The BDLC state table records the current state into the BSVR register. The user's interrupt handler should read the BSVR and vector off.

The BDLC can be placed in what's called a 4x mode and is set to run at a maximum speed of 41.6 kbps. This currently only works for receiving messages, not transmitting them.

The BDLC is variable pulse width protocol and active to passive transitions and vise versa represent a bit. For more information, please refer to the BDLC Technical Reference Manual, BDLCRM/AD.

Symptom;
In our program, the different interrupts are enabled in the output compare interrupt (CLI instruction). If two output compare interrupts are running independently, a software interrupt (IT_SWI) has occurred without a SWI instruction. As can be seen in the explanation, the TMSK1 register is cleared just before the I bit of the CCR. If a "NOP" is implemented between TMSK1 = 0x00 and CLI() instructions, the problem disappears and the software interrupt doesn't occur.

Explanation:
A more general statement of the conditions that cause this to occur is that the source of a previous interrupt is cleared in one instruction and the next instruction is the CLI to re-enable interrupts.

Clearing of the source of the old interrupt occurs on the last cycle of the instruction. (See the cycle by cycle instruction documentation in the CPU12 Reference Manual, CPU12RM/AD). The CLI is a one cycle instruction. The delays to clear the logic of the old interrupt take longer than the CLI processing. (Interrupts are enabled faster than the old source disappears.) The CPU immediately starts a new interrupt process, but when it reaches the point to determine the source, it has now been cleared. The CPU does not know where the interrupt came from and has no pending interrupts, so it takes the default vector which has been defined as SWI.

Solution:
Place a NOP instruction between the interrupt source clear operation and CLI instruction

Example code:

Root cause fix:
This operation will not be changed in current 68HC12 (UDR) parts.

Try this procedure:

BULK_ERASE

MOVB #$06,EEPROG	;Set the bulk Erase
	;EELAT=ERASE=1, ROW=BYTE=0
LDY #$1000
MOVB #$AA, 0, Y
MOVB #$07, EEPROG	;Turn on programming voltage EEPGM
BSR DELAY	;write it for 10 mS
BCLR EEPROG, #$01	;Turn on programming voltage EEPG
BCLR EEPROG, #$02	;Clear EE latch, EELAT=0, Enables
RTS	;Return from subroutine

It is not possible to program the 912D60, F73K mask set EEprom locations with P&E's Prog12s program, but there is no problem with the F68K mask sets.

The BDM lockout feature that was added to the F73K mask sets is controlled from bits in the EEprom control registers. The existing .12p file enables the BDM lockout feature as part of its initialization routine, which immediately locks out the BDM interface.

Solution:

Using a text editor modify the existing .

Change these lines,

WRITE_BYTE=60/000000F0/	;Clear eemcr, prot. off
WRITE_BYTE=00/000000F1/	;Clear eeprot, turn off block protects

To:

WRITE_BYTE=F8/000000F0/	;Clear eemcr, prot. off, disable BDM lockout
WRITE_BYTE=80/000000F1/	;Clear eeprot, turn off block protects,
	;protect shadow register

Remarks:

Having manually edited the .12p file, when attempting to load the modified file into Prog12s, a checksum warning will be issued, but can be ignored.

The primary possibility is that an external device pulls down the reset pin for a long time on any reset. A common way this happens is that the customer has put an external capacitor on the reset pin.

From the Technical Summary:

The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than eight E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for about 16 E-clock cycles, then released. Eight E-clock cycles later, it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor.

(end of technical summary quote)

Solution:
To prevent a COP or clock monitor reset from being detected as an external reset, the reset pin must not be held low by external circuitry during a COP or Clock Monitor reset sequence. An external RC power-up delay circuit on the reset pin is not recommended. Circuit charge time can cause the MCU to misinterpret the type of reset that has occurred.

Conversely, for a true external reset to be properly identified, the reset pin must be held low by this reset circuitry for at least 32 cycles.

Two protected blocks are in the 68HC912D60, one in each of the flash modules, but they are both 8 K, so the smallest protected block size is 8 K. Depending on the system requirements, it might be possible to use the 1K EEprom, which has configurable protected block sizes down to 64 bytes.

Two protected blocks are in the 68HC912D60, one in each of the flash modules, but they are both 8 K, so the smallest protected block size is 8 K. Depending on the system requirements, it might be possible to use the 1K EEprom, which has configurable protected block sizes down to 64 bytes.

It only warns programmers to always stay within 10 msecs of programming time. Overstressing an EEPROM cell can result in permanent damage.

Yes. In the 68HC912D60 it is possible to program one flash block while running the flash programming algorithm from the other block.

Try using the following procedure.

PROGRAM

LDX #NAME

PROGBYTE

LDAA 0,X+
BEQ EXIT
MOVB #$02,EEPROG	;Set EELAT bit in EEPROG register
STAA 0,Y+	; Store data byte to LATCH, increment Y
MOVB #$03,EEPROG	; Turn programming voltage on, EEPGM=1
BSR DELAY	;10mSeconds
BCLR EEPROG,#$01	; Turning off programming voltage EEPGM=0
BCLR EEPROG,#$02	; Clear EE Latch, EELAT=0, Enables Read
BRA PROGBYTE

EXIT

RTS

Try this code:

To INITIALIZE:

INIT_EE	MOVB #$BF,EEPROT	;EEPROM available from
		;$1000-$17FF (Blocksize=2048 Bytes)
	MOVB #$FE,EEMCR	;Lock Protect bits (write) and select system clock
	RTS

The algorithms are found in technical summaries or data books for each individual device.

Guaranteed to 10,000 writes across rated temperature range (not just room temp) and 10 years retention.

The typical time for a bulk erase is 10 ms.

Several things might be happening. Make sure that the jumper on W7 is applied to pins 1 and 2. This connects the V_FP pin on the microcontroller to the V_PP input header W8 on the board.

If that is not the problem, and you are using SDBUG12 with the Serial Debug Interface, try resetting the part to see if the proper values are displayed. There are a few glitches in some versions of this software which can cause the wrong values to be displayed on the screen when displaying the Flash memory and manipulating the Flash control registers. Resetting the part will cause SDBUG12 to reload all values for display, thus clearing up the problem.

The E or P clock (same rate) is the basis for the SPI clock. The divider for this rate is a maximum of 8-bits (256). The minimum divider is 2, resulting in a maximum SPI clock of 4 MHz for an 8 MHz E clock rate.

The Flash EEPROM on 68HC912 products are guaranteed for 100 write/erase cycles.

The maximum programming voltage (V_FP) allowed for the Flash module :

For masks 1H91F, 3H91F is 11.4 - 11.8 Volts.

Higher voltages can cause premature failure of the Flash module.

For all other masks, use 11.4 - 12.6 V (12 V +-5%)

See the errata for the particular mask set you are using.

If you compute SCIbaud = MCLOCK / 16 * BR where BR = 1 and Eclock = 8MHz, gives a maximum transfer rate of 500 K. Theoretically this is the fastest transfer rate.

Use the following steps.

INIT_SCI

MOVB #$26,SC0BDL	;Set the Baud Rate
MOVB #$00,SC0CR1
MOVB #$0C,SC0CR2
LDAA #$0C
STAA SC0CR2
RTS

The following routine can be used to send 256 points stored in the array DATA to the SCI.

TRANSMIT

LDX

#DATA

TR0

BRCLR	SCOSR2,$80,TR0	;Monitor the Transmit empty flag
MOVB	1,X,SC0DRL	;Move data to the SCI register
INX
CPX	#DATA+256
BNE	TR0	;If data is collected exit
RTS

You can get up to 4 MHz on an output compare channel on the 68HC12 devices, if you utilize the automatic timer counter reset feature of this timer module.

The following is a code segment which sets up OC0 to toggle and OC7 to reset the timer counter automatically when the TC7 value is reached.

clr	PORTT
ldaa	#$01
staa	DDRT
bset	TIOS,$81
ldaa	#$01	;Use Channel 0
staa	OC7M
staa	OC7D
ldaa	#10010000Q	;Fast flag clear - unneeded here
staa	TSCR	;Enables Timer
ldaa	#$00
staa	TCTL1
ldaa	#$01
staa	TCTL2	;Set channel 1 to toggle
ldaa	#00000000Q	;What channels can cause IRQ
staa	TMSK1	; (none here)
ldaa	#$08
staa	TMSK2
ldd	#$0000
std	TC0
ldd	#$0002
std	TC7

With the above code segment (and an 8 MHz E-clock), the following values can be achieved:

TC0 Value TC7 Value Frequency at OC0
$02	$04	1.6 MHz
$02	$03	2.0 MHz (75% duty cycle)
$01	$03	2.0 MHz (50% duty cycle)
$00	$03	2.0 MHz (25% duty cycle)
$01	$02	2.6 MHz (66% duty cycle)
$00	$02	2.6 MHz (33% duty cycle)
$00	$01	4 MHz (50% duty cycle)

The SCI baud rate is based on the M Clock in the 68HC812A4 device, and P Clock in the 68HC12B32 device. Both of these clocks are the same frequency as the E Clock (crystal frequency/2). The following formula can be used to calculate baud rates:

Desired Baud Rate = MCLOCK / 16 * BR

Where BR is the value written to bits SBR[12:0] in the baud rate control registers. There is a table in the technical summaries for each device which shows the BR values for standard baud rates.

This handler and main routine will help you start. The main program is responsible for monitoring "COMP_FLAG" and using the data properly.

ATOD_HANDLER

CPY #data+512	;Check data overrun.
BEQ SETFLAG	;by comparing the pointer by 512
	;assurance to 256 points is established.
	;and no more conversions will be taken
LDAA ATDSTAT,X	;check CCF0
ANDA #$01	;mask value in AN0
CMPA #$01	;check proper value
BNE OUTRTI
;---if program gets here channel one is the interrupt---
LDD ADR0H	;Fetch A/D 10-bit value
STY 0,Y	;Store into DATA array
INY	;walk the pointer by one
INY	;walk the pointer by one
LDAA #$ff	;start one more
STAA ATDSTAT,X
BRA OUTRTI

SETFLAG

LDAA #1

STAA COMP_FLAG

;when low acquisition just started

;Announce completion to main

OUTRTI

RTI

Currently there is no 10-bit test carried out on the 912DG128. The 8-bit A2D tests are carried out for 1 lsb accuracy at 8-bit resolution (input of (V_RH-V_RL)/2 + (V_RH-V_RL)/512) with the acceptable results being $80 or $81.

If the PLL is used, a filter capacitor should always be used with CGMXFC. If the PLL is not used, this pin can be connected to V_SS.

Users are welcome to use the following routine.

CONVERT

PSHA
LDAA #$FF	;start acquisition
STAA ATDSTAT
STAA ATDSTAT

WAIT_AD0

LDAA ATDSTAT
ANDA #$01
CMPA #$01
BNE WAIT_AD0	;wait_ad
LDAB ADR0H	;Fetched 8 bits only
LDD ADR0H	;Fetched 10 bits.
STD 0,Y	;IY is a pointer to data array
PULA	;Restore REG A
RTS

INIT_AD

LDAA #$80
STAA ATDCTL2	;Power up the A/D module
JSR delay_ad	;wait to stabilize
LDAA #$70
STAA ATDCTL5	;run in normal mode
LDAA #$81	;enable 10 bit A/D
STAA ATDCTL4	;Fastest acquisition mode
RTS

Currently Motorola has allocated testers that test an A/D to 8-bit resolution that being a limiting factor for testing current product. Testers are being qualified to test the 68HC12's A/D at 10-bit resolution. However, if users want to use 10-bit mode, refer to the 68HC12 A/D initialization code FAQ.

The oscillator frequency is divided by two to generate E clock and P clock. P clock then feeds into the ATD prescalers and then another divide-by-two stage. Therefore, when the user sets the A/D prescaler bits to zeros, the P clock frequency is divided by two. When the micro is running at 8 MHz E clock, the ATD clock becomes 2 MHz.

2 times the maximum frequency of a signal, including noise.

read input capture register
read input capture holding register
Read pulse accumulator holding register

If a pulse is received in between reading the input capture register and input capture holding register then the pulse accumulator holding register will read one pulse too many. (e.g. if a read of the input capture register has a timer value for the ninth pulse because another pulse was received, the pulse accumulator holding register will read 10.)

Explanation:
Reading the input capture holding register latches the pulse accumulator register to the pulse accumulator holding register. This will be mismatched due to the next pulse being received.

Solution:
The software should:

read input capture register and store in a temporary variable
read input capture holding register
read input capture register and compare with temporary variable
if these values are equal then
read pulse accumulator holding register
else continue reading and comparing until they are equal

Remarks:
This is not a malfunction the device was designed to function in this way.

• We do not believe there is a problem with the oscillator and Murata resonators. Motorola is working with Murata to generate data to resolve this.
• In the Murata tests, a strongly driven E-clock signal is output and measured with a scope probe. We believe that the scope probe may be causing the problem, coupling noise into the oscillator.
• There are no customers in volume production at this time. Our major volume customer is using a 4 MHz crystal without problems.
• The oscillator can be affected by power supply ripple so good board design and supply decoupling are essential.

If your crystal circuitry is not starting reliably, it's probably due to added capacitance on C1 and C2. Motorola's recommended value given in chapter 2 of the 68HC11 Reference Manual (M68HC11RM/AD), is between 5 pF and 25 pF. If the PCB's stray capacitance is higher than about 15 pF, The crystal total impedance can be marginal and not provide enough gain for the circuit to start. A good fix is to reduce the value from the load capacitors.

Yes, but the reset must be a power-on reset, not just a pin reset. Incidently, indication of whether security entry is successful can be monitored by checking address $40, bit 6. If it is high, then security entry was satisfied

There are two general scenarios when entering monitor mode: when there is V_TST (~ V_DD + 2V) applied to IRQ or when V_DD or V_SS is applied to IRQ. The first case needs to be done when the reset vector ($FFFE-$FFFF) is not blank but V_TST can also be applied when the reset vector is blank.

When the reset vector is blank as in the case when the part is unprogrammed and the entire FLASH is blank, monitor mode can be entered with V_TST, V_DD or V_SS applied to IRQ. If V_TST is applied, port C settings are enforced to enter monitor mode. The port C requirements are C0 must be tied to V_DD, C1 must be tied to V_SS, and the state of C3 determines whether the internal frequency will be the external clock divided by 2 (C3 low) or the external clock divided by 4 (C3 high). If V_DD is applied, then the internal frequency is the external (oscillator) frequency divided by 4, and the communication rate is the internal frequency divided by 256, or the external frequency divided by 1024. If V_SS is applied to IRQ with the reset vector blank, then the PLL is automatically engaged. The PLL will set the internal frequency to 2.4576 MHz when the external clock (crystal or oscillator) is 32.768 kHz. Again the communication rate is the internal frequency divided by 256 - in this case 9600 bps. In either of these latter two situations, port C pins do not have to be set to any particular polarity and, in fact, port C3 has no effect on internal frequency.

If the reset vector is non-zero, as is the case when the part has already been programmed, then V_TST must be applied to IRQ and the communication rate is the internal frequency divided by 256. The state of port C3 determines the internal frequency and the communication rate.

After failing security, the monitor is still active and one can still execute the six monitor mode commands, which will allow one to download and execute a RAM routine. The FLASH array is still secured and cannot be read, however, it can be bulk erased. By performing a bulk erase in the RAM routine, one can clear the FLASH array and the part can be reprogrammed and re-used.

The 68HC908GP20 does not have open-drain general I/O outputs available. The SPI output drivers have open-drain capabilities, but that is only with the SPI enabled (no digital output open-drain available).

One can erase the FLASH after entering monitor mode and failing security by then loading a RAM routine that executes a bulk erase. A bulk erase is the only FLASH access operation that can be performed when security entry fails. The RAM routine should follow the bulk erase procedure outlined in the 68HC908GP20 documentation.

No. The 68HC908GP20 does not have an external bus, so mapping an external peripheral into its address space is not possible. Incidentally, trying to execute from an address in an unimplemented area of memory will cause an illegal address reset.

Yes. Blank parts can enter monitor mode with IRQ low, thereby automatically causing the PLL to generate a 2.4576 MHz internal frequency. This frequency will not only allow 9600 baud communication over PTA0, it will also generate an adequate (> 1.8 MHz) charge pump frequency to program FLASH.

For in-circuit reprogramming, it is up to the user's code to enable the PLL to generate an internal frequency of at least 2 MHz and one that will facilitate serial communication at a standard baud rate.

Section 23.13, page 391, of the Advanced Data Book, rev. 2.0, shows the ADC specifications. The ADC is accurate to (+/-) 1 LSB, provided appropriate bypassing is implemented.

Section 23.13, page 391, of the Advanced Data Book, rev. 2.0, shows the ADC specifications. The ADC is accurate to (+/-) 1 LSB, provided appropriate bypassing is implemented.

No. The only thing that is protected and can't be read is the FLASH ROM.

The process of programming a FLASH array requires that the entire array be put in a Write mode and therefore one cannot execute (read) from an array that is being programmed. Since the 68HC908GP20/32 has only a single array, program execution must occur out of RAM. By contrast, the 68HC908AZ60 has two arrays so one array can be programmed by code executed out of the other array.

The reference clock for the SCI can be either CGMXCLK or the internal bus clock, depending on the setting of the SCIBDSRC bit in CONFIG2. SCI baud rate is defined as (selected reference clock frequency) / (64 * PD * BD), where PD and BD are the prescaler divisor and the baud rate divisor, respectively. This allows a theoretical maximum baud rate at V_DD = 5V to be 32.8 MHz / (64 * 1 * 1) = 512.5 kbps.

The reference clock for the SCI can be either CGMXCLK or the internal bus clock, depending on the setting of the SCIBDSRC bit in CONFIG2. SCI baud rate is defined as (selected reference clock frequency) / (64 * PD * BD), where PD and BD are the prescaler divisor and the baud rate divisor, respectively. This allows a theoretical maximum baud rate at V_DD = 5V to be 32.8 MHz / (64 * 1 * 1) = 512.5 kbps.

Vrefh and Vrefl are set via the V_DDad and B_SSAd pins, respectively. These pins must be at the same voltage potential as V_DD and V_SS, respectively.

To obtain 100 kHz signal frequency, you are probably programming the modulo register (T1MODH/T1MODL) with $0048 (72 decimal). The CH1F bit will never get set for channel register values that are higher than the value in the modulo registers, because the timer counter can only take on values up to and including the value in the modulo registers. Therefore, if you are comparing the timer value to an always higher value in the channel registers, then a compare event (toggle, set or clear the output) will never occur and you'll see a 100% duty cycle.

To obtain 100 kHz signal frequency, you are probably programming the modulo register (T1MODH/T1MODL) with $0048 (72 decimal). The CH1F bit will never get set for channel register values that are higher than the value in the modulo registers, because the timer counter can only take on values up to and including the value in the modulo registers. Therefore, if you are comparing the timer value to an always higher value in the channel registers, then a compare event (toggle, set or clear the output) will never occur and you'll see a 100% duty cycle.

In user mode, the internal frequency of an 68HC08 is always the external frequency (CGMXCLK) or the PLL frequency (CGMVCLK) divided by 4.

The TIM08 manual states that in buffered PWM mode the unused channel reverts to port control.

There are some gotchas to consider for use of the PLL with a 32.768 kHz crystal.

1. The CGMXFC pin must be used with an appropriate capacitor, typically 0.47 uF
2. Good decoupling practices must be observed. Especially important: that the V_DDa pin has its own decoupling capacitor (~0.01 uF) that is placed as close to the package as possible.
3. Placing the correct values in the CGM registers.

A code segment follows:

;Assembler equates

PCTL	EQU	$36
PBWC	EQU	$37
PMSH	EQU	$38
PMSL	EQU	$39
PMRS	EQU	$3A
PMDS	EQU	$3B
BCS	EQU	$04
PLLON	EQU	$05
AUTO	EQU	$07

-----------------------------------; Set it up

	BCLR	BCS,PCTL	;Select external clock
	BCLR	PLLON,PCTL	;Turn PLL off
	CLR	PCTL	;Clear P and E
	MOV	#$1,PMDS
	MOV	#$0,PMSH
	MOV	#$F4,PMSL
	MOV	#$D0,PMRS
	LDA	PCTL

--------------------------------------;Turn it on

	BSET	AUTO,PBWC	;Automatic bandwidth control
	BSET	PLLON,PCTL	;Turn PLL on
	BRCLR	LOCK,PBWC,*	;Wait for lock
	BSET	BCS,PCTL	;Select PLL output as base clock

There is no such voltage vs. frequency curve. The specs in the GRS are given for V_DD voltages of 3 V and 5 V (+/-10%). The acceptable range for bus frequency is given for each of these two voltage levels. Operation at other voltage levels and frequencies above those given is not specified.

There is no such voltage vs. frequency curve. The specs in the GRS are given for V_DD voltages of 3 V and 5 V (+/-10%). The acceptable range for bus frequency is given for each of these two voltage levels. Operation at other voltage levels and frequencies above those given is not specified.

This PLL requires a reference clock of 16 to 100 kHz. The maximum divider value is 15, so the maximum external clock source you can use with the PLL is 1.5 MHz.

The programming voltage for both parts is 16.5 volts.

With a 32.768 kHz crystal, the expected power-on delay is 497 ms.

4064 * tcyc = 497 ms , where tcyc = 8192 Hz (32.768 kHz/4)

The PLL is on at reset, but the BCS (base clock select) is cleared, making the 32.768 kHz crystal the clock source for the bus.

There are only 2 options for clock source for the 68HC908GP20. Either a crystal in the range of 30-100 kHz or an external oscillator in the range of DC - 32.8 MHz (PLL disabled) or 30 kHz - 1.5 MHz (PLL enabled). The PLL can be used to bump up either of these two clock references to a resulting internal frequency up to 8.2 MHz @ V_DD = 5 V (4.1 MHz @ V_DD = 3.3 V). See section 7.4.6 of the 68HC908GP20 documentation for a procedure on how to program the PLL.

BDRxD is the BDLC' s receive pin and, out of reset, is set as high input impedance. It is best to tie this pin low (via a low value resistor) to avoid the possibility of accidentally ' awakening' the BDLC module. This is also the best way to draw the least amount of current.

BDTxD is the BDLC' s transmit pin and as such is an output driven by the MCU. It is best to leave this floating rather than tying high or low.

Summary :
BDRxD = tie to V_SS via a low value resistor
BDTxD = leave floating

Run I_DD with all modules operating is approximately 27 mA @ V_DD = 5.5 V, F_BUS = 8 MHz.

A rough estimate as to where current is going is as follows:

Module	IDD (mA)
None	15
SCI, SPI, Timer	<1
A/D	6
PLL	4-5

There is no problem with retaining writes to the Config Registers in code submitted for the ROM version of the 68HC908AZ60.

These registers are not implemented on the 68HC08AZ32 and have no effect.

There is no problem with retaining writes to the Config Registers in code submitted for the ROM version of the 68HC908AZ60.

These registers are not implemented on the 68HC08AZ32 and have no effect.

Symptom:
The original 68HC08 secure monitor could not reliably communicate with a PC serial port when the 68HC08 was clocked with a 4-, 8-, or 16- MHz crystal. The user was forced to use a 4.9152 MHz crystal to guarantee reliable operation. This crystal is not a popular choice with customers using the MSCAN module.

Solution:
Monitor Mode on 1J66D (68HC08AZ60) and 1J61D (68HC908AZ60) differs from previous mask sets in one area, baud rate. The next table shows the baud rates which are available for a range of crystals. The table lists the two baud rates the 68HC08 can produce using a given crystal, and the closest baud rate which a standard PC communication port can reliably generate. The generated baud rates were chosen so that it was still possible to communicate with the 68HC08 using 4.9152 MHZ and 4.194 MHz crystals.

Remarks:
An IBM-compatible PC communication port can generate required baud rates for all frequencies listed in the previous list.

There is no bit to say there is a mismatch. Redundant mode works by combining the charge on the two cells with some analog circuitry. This combined charge is then used to determine if it is a 0 or 1.

Both "unused" and "unimplemented" bits or bytes of memory generally mean that they do not exist and therefore cannot be used. A "reserved" location, however, means that it contains data which may dynamically change based on a function put on the device for factory test or diagnostic purposes. Writing to, or reading from, any of these types of locations may not damage the part or cause the part to malfunction, but the user is urged not to use these locations.

Both unused" and "unimplemented" bits or bytes of memory generally mean that they do not exist and therefore cannot be used. A "reserved" location, however, means that it contains data which may dynamically change based on a function put on the device for factory test or diagnostic purposes. Writing to, or reading from, any of these types of locations may not damage the part or cause the part to malfunction, but the user is urged not to use these locations.

The erased state of EPROM, OTPROM and EEPROM varies from device to device. In most EPROM and OTPROM microcontrollers, an unprogrammed or erased state has value $00. This is true in the 68HC705B16N/B32, 68HC705C8A/C9A, 68HC705J1A, 68HC705JJ7 (including the PEP), 68HC705KJ1, 68HC705P6A, and others. An exception to this general rule is the 68HC705L16 which has an erased state of $FF.

The erased state of EEPROM in various devices is more complicated. In the 68HC705B16(N) and the 68HC705B32, while the EPROM has an erased state of $00, the small block of EEPROM in each of these devices has an erased state of $FF. The 68HC805P18 has two classifications of EEPROM memory, a 128-byte block of programming memory and a 8064-byte block of user EEPROM. The programming EEPROM's erased state is $FF while the user EEPROM's erased state is $00. In the 68HC805K3, the erased state for both the main EEPROM array and the personality EEPROM (PEEP) is $00.

In the A family of 68HC08's (i.e., 68HC908Az60, 68HC908AS60, etc.), the erased state of the large flash block(s) is $00, while the erased state of the smaller EEPROM block(s) is $FF. This is consistent with most flash arrays, where the erased state is $00. To be safe, check the data book to make sure of the erased state of memory for whatever device you are using.

In general, if an EEPROM array is the main user array for the device, then its erased state is $00. If the EEPROM is a smaller block of programming memory (not personality EPROM), then its erased state is $FF. This table summarizes memory types and erased states for the more popular Motorola devices.

PEP, or PEPROM, stands for Personality EPROM and is used to store user data or variables in non-volatile memory. This array has the advantage of being bit-addressable and is used primarily to store a serial or ID number that is unique to each individual unit. There are 64 bits of PEP in the 68HC705JJ7*, arranged as 8 bytes of 8 bits per byte. These bits are read serially by writing the bit location to be read into the PEPROM's Bit Select Register (PEBSR) and reading the state of the PEDATA bit of the PEPROM Status/Control Register (PESCR). To read a bit of the array, the byte is specified by assigning the binary value (000 to 111) of the byte to bits b5-b3 of the PEBSR, and then specifying the bit position (000 to 111) with bits b2-b0 of PEBSR. This completely identifies one and only one bit position of the array and its value can then be determined by reading PESCR's PEDATA bit.

Programming these bits is done with the same reference method where the bit position to be set is first specified in the PEBSR register. Then the PEPGM and CPEN bits of the PESCR are set and held for a specified delay time and then cleared again (see tEPGM in the Control Timing Specifications for the device). Erasing can be performed only on windowed devices with the use of an ultraviolet light. Consult the appropriate data manual for more detailed discussion on PEPROM.

*Also includes other family members such as JP7, SP7 and SJ7.

PEEP, or PEEPROM, stands for Personality EEPROM and is used to store user data or variables in non-volatile memory. This array has the advantage of being bit-addressable and is used primarily to store a serial or ID number that is unique to each individual unit. There are 128 bits of PEEP in the 68HC805K3 arranged as 16 bytes of 8 bits per byte. These bits are read serially by writing the bit location to be read into the PEEPROM's Bit Select Register (PEBSR) and reading the state of the PEDATA bit of the PEEPROM Status/Control Register (PESCR). To read a bit of the array, the byte is specified by assigning the binary value (0000 to 1111) of the byte to bits b6-b3 of the PEBSR, and then specifying the bit position (000 to 111) with bits b2-b0 of PEBSR. This completely identifies one and only one bit position of the array and its value can then be determined by reading PESCR's PEDATA bit.

Programming these bits is done with the same reference method where the bit position to be set is first specified in the PEBSR register. Then the PEPGM and CPEN bits of the PESCR are set and held for a specified delay time and then cleared again (see tEPGM in the Control Timing Specifications for the device). Erasing can be performed with the use of the PEBYTE (byte level) and PEBULK (entire array). Consult the appropriate data manual for more detailed discussion on PEEPROM.

• MC68HC705J1A, standard version of J1A
• MC68HRC705J1A, RC Oscillator Mask Option: For greater cost reduction, the RC oscillator mask option allows an external resistor to drive the on-chip oscillator.
• MC68HSC705J1A, High-speed Version: Allows a maximum internal operating frequency of 4MHz.
• MC68HSR705J1A, High-speed RC Oscillator Version: Combines the features of the HSC705J1A and the HRC705J1A.
• MC68HC705KJ1, 16-pin version of the 68HC705J1A.

It may be advantageous to get into another mode of operation other than user mode after the device is programmed. When this is the case and there is no concern about code secrecy, do not set security. For example, the Load-RAM-and-Execute capability of the bootloader mode is useful as a debugging or failure analysis tool for the micro or a peripheral circuit. A test program can be loaded into, and executed from, RAM without having to alter or change out the existing program code. If security is set, then entry into bootloader mode is disabled and one would not have the capability of loading a RAM routine unless it is built into the program code.

In units that have a low-voltage data-retention mode (i.e., C8A, J1A, J2, K1, P9, etc.), contents of RAM can be preserved at V_DD voltages down to 2.0 V. To get into this mode, the reset line must be brought low (and kept low during this mode) and then V_DD can be lowered to as low as 2.0 V. For controllers that do not have this mode, the only sure way of maintaining RAM content is to keep the device active either in standard operating mode or in a low-power mode (wait or stop). During active operation, the supply voltage of the device cannot be reduced below the specified V_DD limits of the device, usually 4.5 V unless low voltage operation is supported. See the section on DC electrical specifications in the technical data book for your particular device.

The SEC, or Security, bit is located in the Option register and is usually implemented in the same type of memory as the program memory (i.e., EPROM, EEPROM). It is therefore non-volatile and its value remains intact during power down. Its purpose is to prevent unwanted examination of program memory by disabling entry into any mode other than user mode. This bit, which is set to turn security protection on, is programmed in the same manner and at the same time that the program array is programmed.

A cold reset, in this context, is defined as a low-to-high transition on the V_DD line. The processor does nothing to RAM as part of its reset or start-up sequence. Therefore, the state of RAM is indeterminate after a cold reset, and the user should not depend on RAM data being retained or changed if power is removed for any length of time. On a warm reset, which can be caused by an external low-to-high transition on the RESET line, a COP time-out, an LVI reset*, or an illegal opcode/address reset, the state of RAM is retained as power has not been interrupted.

During transitions to (from) both WAIT and STOP modes, all registers, memory and I/O states remain unchanged. Therefore, the state of RAM is unaffected by use of these two low-power modes.

*Assumes that V_DD has reduced to a level that causes the LVI reset, but has not dropped to a level that stops the device. See the documentation section on DC electrical specifications in the technical data book for the device being used.

All instructions that support indexed addressing mode support the 16-bit H:X register for the index register. These instructions are: ADC, ADD, AND, ASL, ASR, BIT, CLR, CMP, COM, CPX, DBNZ, DEC, EOR, INC, JMP, JSR, LDA, LDX, LSL, LSR, NEG, ORA, ROL, ROR, SBC, STA, STX, SUB, and TST. In addition, there are two basic instructions which support the automatic incrementing of the H:X register. The CBEQ instruction supports the 16-bit Indexed, No or 8-bit Offset with Post Increment (IX1+) mode which post increments the H:X index register after the compare. Also, two of the four variations of the MOV instructions, Memory to Memory, 16-bit Indexed to Direct with Post Increment and Memory to Memory, Direct to 16-bit Indexed with Post Increment support the use of the H:X index register with post increment.

Other instructions which utilize this register pair are AIX (increments H:X by an immediate value), CPHX (compares H:X with 16-bit value in memory), LDHX (loads H:X), STHX (stores H:X), TSX (transfers stack pointer to H:X) and TXS (transfers H:X to stack pointer). Instructions that act on the H register separately are CLRH, PSHH and PULH.

BSET and BLCR are Read-Modify-Write instructions. Write-only registers will read back undefined data. Therefore, a Read-Modify-Write operation will read undefined data, modify it as appropriate, and then write it back to the register. Because the original data is undefined, the data written back will be undefined.

The I bit is set after reset and is cleared by the CLI instruction. When there is a pending interrupt during or before the CLI instruction execution, the next instruction is fetched by the CPU but is not executed. The interrupt routine then runs. This has confused some people working with bus analyzers who are surprised to see the next instruction apparently run and then the interrupt routine run.

Push instructions have been added which facilitate storage of the accumulator (PSHA), the X register (PSHX), and the H register (PSHH). Conversely, corresponding pull instructions (PULA, PULX, and PULH) have been added to load each of these registers with the value on the top of the stack. Direct transfer of register content between the stack pointer and the H:X register has also been added with the TSX and the TXS instructions.

All instructions that support indexed addressing mode for the (H:X) index register have been expanded to support one or both stack pointer addressing modes, except for JMP and JSR. This allows use of the instruction with the index relative to the content of the 16-bit stack pointer rather than the 16-bit H:X register. These instructions are: ADC*, ADD*, AND*, ASL, ASR, BIT*, CLR, CMP*, COM, CPX*, DBNZ, DEC, EOR*, INC, LDA*, LDX*, LSL, LSR, NEG, ORA*, ROL, ROR, SBC*, STA*, STX*, SUB* and TST. Also, the CBEQ instruction supports the Stack Pointer, 8-bit offset mode. Note that this instruction which has the form 'CBEQ offset, SP, reladr' does not automatically increment the stack pointer as it does the H:X register in its IX+ addressing mode.

*Supports both Stack Pointer, 8-bit offset (SP1) mode and Stack Pointer, 16-bit offset (SP2) mode, while the others support only Stack Pointer, 8-bit offset mode.

The V bit is used primarily in signed arithmetic and is set when a twos complement overflow occurs as a result of an operation. An overflow, as used in this context, can occur after an addition or a subtraction. A general rule to determine whether the V bit gets set as a result of an addition is that if both operators are of the same sign, where a negative value always has bit 7 set, and the result is of the other sign, then the V bit will be set. It would not get set under any other conditions. For example, if $80 is added to $FF, then the result is $7F with the V bit set. If $01 is added to $7F, then the result is $80 and the V bit is set. For subtraction, the V bit is set if the result of the subtraction and the subtrahend is of the same sign and the minuend is of the other sign. In other words, the subtraction can be rearranged to form an addition, where the result is added to the value to the right of the minus sign and produces the value to the left of the minus sign. In this case, the previous rule for V bit setting for addition is followed.

This flag is useful when used in conjunction with the N bit, which gets set if the result of an operation is negative. Together, these two bits can indicate whether the result of an operation is really a positive value greater than 127 or a negative value. If the exclusive-ORing of these two bits results in a 0, then the final value is positive. If the result is 1 then the final value is negative. For example, if in the above example, $80 + $FF = $7F. The V bit gets set but the N bit is cleared, and the exclusive-OR of these two bits is 1 signifying a negative final value. But $7F is interpreted as +127 in signed arithmetic, which would be incorrect as -128 [$80] + (-1) [$FF] = -129. Another example would be subtracting $80 from $7F and getting $FF. Both V and N get set as a result of this operation which would exclusive-OR to produce a zero, signifying a positive value. It would be incorrect to interpret the result $FF as -1, as 127 - (-128)[$80] = 255 [$FF unsigned]. By knowing and using these two rules, you'll be sure to interpret signed arithmetic results correctly.

The PSHX instruction is used to push the contents of the X registers onto the stack. As a result of this operation, the stack pointer is decremented by 1. Often this instruction is accompanied by the PSHH instruction, which pushes the content of the H register onto the stack, to free the entire 16-bit index register for other use. In contrast to push instructions, the TXS instruction transfers the content of the index (H:X) register to the stack pointer, not the stack. The result of this operation causes the stack pointer to point to a location specified by the contents of the index register. Sometimes this is done when the index register is indexing through one set of data and it is desirable to index through another set of data at the same time. Here the stack pointer can be used as an index. However, great care should be taken when using the TXS instruction so as not to lose the content of the stack.

The 16-pin 68HC705KJ1 is software compatible with the 20-pin 68HC705J1A.

• The 68HC705KJ1 has 10 I/O vs 14 I/O for the 68HC705J1A
  • 68HC705KJ1 port B has only two of its six I/O ports available externally. Configure the four unused I/O ports as inputs to ensure proper termination.
• The 68HC705J1A has four pins capable of 10 mA sink, the 68HC705KJ1 has all 10 of its I/O capable of 10ma sink
• The 68HC705KJ1 has an improved oscillator design for more robust noise immunity
• The 68HC705KJ1 has a version optimized for low power operation using 32 kHz crystals (MC68HLC705KJ1)

Pay attention to the seven key differences.

No, the 68HC705C8A does not have an illegal address reset. Some promotional literature for the device incorrectly attributed this feature to the 68HC705C8A. The data book is correct.

The stack is a data structure that could easily be implemented in a user program, which would perform some or all of the built-in features for using the stack in the 68HC08. The following is a simplified outline for a stack implementation, which could be modified or enhanced depending on specific requirements. This stack assumes an address decrement to get the next address to be accessed by the stack.

1. Assume and assign a fixed size for the stack and allocate this amount of RAM.
2. Allocate a single-byte RAM location for the variable StackPointer. This will be an 8-bit value which represents the current location of the stack pointer. To conform to the 68HC05 and 68HC08 convention, the current location will always be the next location that a value will be stored if a store is implemented. In this implementation, the stack is limited to an 8-bit address value, but could be expanded to 16-bits as in the 68HC08.
3. Allocate a single-byte RAM location for the variable StackStart. This will be an 8-bit value which represents the first location of the stack.
4. Allocate a single-byte RAM location for the stack status bytes. This byte will contain as a minimum a bit to represent the two Boolean variables StackFull and StackEmpty.
5. Write functions to access the stack such as the following:
   1. Push - Checks to see if the StackPointer is full and, if not, stores the value in the accumulator (PushA) or in the index register (PushX) to the next location on the stack. This function, as well as others dealing with this stack, should return a value indicating success or failure implementing the request. The stack should be decremented after the push operation.
   2. Pop - Increments the StackPointer and if an underflow situation doesn't exist, then loads the accumulator (PopA) or the index register (PopX) with the value contained in the location referenced by the StackPointer.
   3. ResetStackPointer - Sets the stack pointer to the StackStart address.
6. Other functions can be added as necessary such as TSX (transfer the value of the stack to the index register. Note that a function that would emulate the 68HC08's TXS instruction (transfer content of the index register to the stack pointer) may compromise the integrity of the stack if used improperly. A function that would emulate the 68HC08's stack pointer with 8-bit offset mode could be very useful when used in conjunction with the index register to compare or manipulate two sets of data.

Even though one must sacrifice code relocatability, the absolute addressing JMP and JSR instructions provide much more flexibility than their relative addressing counterparts. Each of these two instructions supports five addressing modes -- direct, extended, indexed, indexed with 8-bit offset, and indexed with 16-bit offset -- with extended addressing being by far the most commonly used mode for these instructions.

The use of direct addressing jumps is usually transparent to the programmer unless he is counting instruction bytes. This mode reduces the instruction length from three bytes for extended addressing to two bytes, since the jump destination is always in the first page of memory ($00-$FF).

Indexed addressing with no offset, an 8-bit offset, or a 16-bit offset is used to take different actions depending upon a data value or its location. For example, the following code would cause consecutive jumps to an array of different subroutines using the indexed with 16-bit offset addressing mode. This routine is a simplification and real code would probably contain selection criteria to determine which subroutines to execute depending upon certain existing conditions.

Even though one must sacrifice code relocatability, the absolute addressing JMP and JSR instructions provide much more flexibility than their relative addressing counterparts. Each of these two instructions supports five addressing modes -- direct, extended, indexed, indexed with 8-bit offset, and indexed with 16-bit offset -- with extended addressing being by far the most commonly used mode for these instructions.

The use of direct addressing jumps is usually transparent to the programmer unless he is counting instruction bytes. This mode reduces the instruction length from three bytes for extended addressing to two bytes, since the jump destination is always in the first page of memory ($00-$FF).

Indexed addressing with no offset, an 8-bit offset, or a 16-bit offset is used to take different actions depending upon a data value or its location. For example, the following code would cause consecutive jumps to an array of different subroutines using the indexed with 16-bit offset addressing mode. This routine is a simplification and real code would probably contain selection criteria to determine which subroutines to execute depending upon certain existing conditions.

It may be desirable to manipulate a register or memory without modifying the condition code register. This would be the case if a flag-setting instruction is intended to cause a later action like a conditional branch, but you want another data manipulation to take place in the meantime. It is worth noting which instructions may be used that modify a register or memory without altering any of the flags of the condition code register. They are:

1. Add immediate value to stack pointer or (H:X) index register (AIS, AIX)
2. Bit set and bit clear (BSET, BCLR)
3. Decrement and branch if not 0 (DBNZ)
4. Nibble swap accumulator (NSA)
5. Pushes and pulls (PSHA, PULA, PSHH, PULH, PSHX, PULX)
6. Register transfers (TAP, TPA, TAX, TXA, TSX and TXS)

This may not be an adequate set of instructions to perform the desired data manipulation. If this is the case, then use the TPA and then PSHA to save the condition code register for the later conditional branch, or use the SWI and perform the desired operation in the interrupt service routine. Upon return from interrupt, the condition code register will be restored.

The five flags of the 68HC05's condition code register, which is a subset of those found in the 68HC08, are half-carry (H), interrupt mask (I), negative (N), zero (Z) and carry/borrow (C). The half-carry flag is set whenever there is a carry from the low-order nibble (b3-b0) to the high-order nibble (b7-b4) after an execution of a BCD instruction. The only two instructions which can cause this flag to set are ADD and ADC (the MUL instruction automatically clears this flag, and the RTI overwrites the entire register). With the use of this bit, one can decimal-adjust the 8-bit value in the accumulator after execution of each of these two instructions (ADD or ADC) to preserve a BCD value. The following table shows what action would be taken to decimal correct based on the result of an add or add-with-carry operation, and the status of the C and H flags.

Initial C-bit Value	Value of b7-b4 in Accum.	Initial H-bit Value	Value of b3-b0 in Accum.	Correction Factor	Corrected C-bit Value
0	0-9	0	0-9	00	0
0	0-8	0	A-F	06	0
0	0-9	1	0-3	06	0
0	A-F	0	0-9	60	1
0	9-F	0	A-F	66	1
0	A-F	1	0-3	66	1
1	0-2	0	0-9	60	1
1	0-2	0	A-F	66	1
1	0-3	1	0-3	66	1

The I bit of the condition code register determines whether interrupts are serviced. It serves as a global interrupt mask and when this bit is set, then only the SWI will be serviced while the rest of the interrupts in the system become disabled. Instructions that affect this bit are CLI, RTI, SEI, STOP, SWI, and WAIT. The CLI, WAIT, and STOP clear this bit, while the SEI and SWI set it. The RTI overwrites the entire register. The CLI and the SEI are the two primary instructions to programmatically clear and set the I bit, respectively.

The N bit is set when the result of an operation sets bit 7 of the operand. Its primary use is with signed arithmetic and it signifies that the result of an operation is a negative number. It can also be used as a flag for normal bit testing of bit 7. Instructions which affect (set or clear) this bit are:

1. Arithmetic operations (adds, subtracts, increments, decrements)

2. Logical operations (AND, OR, and EOR)

3. Bit shifts and test

4. Complements and negates

5. Compares and (byte) test

6. Loads and stores

7. RTI

The clear (CLR) and the logical shift right (LSR) instructions always clear the N bit.

The Z bit of the condition code register is used extensively as a check to see if the result of an operation is zero. It is the flag commonly used in loop constructs to determine whether a loop should be repeated or exited. Instructions which affect this bit are exactly the same ones that affect the N bit, except that the CLR instruction always sets the Z bit and the result of an LSR may set or clear the Z bit.

The C bit of the condition code register is usually used to indicate a carry from an addition or a borrow as a result of a subtraction. It can also be set during bit shift operations, and there are specific instructions just to set or clear the carry bit. Instructions that affect the C bit are:

1. Arithmetic operations (adds and subtracts only)

2. Bit shifts

3. Negates

4. Compares

5. RTI

6. Branch if bit set/clear (BRSET, BRCLR)
   

The clear carry (CLC) and multiply (MUL) always clear the C bit; the set carry (SEC) and complement instructions always set the C bit.

The SWI instruction can be used to make a specific block of code atomic, to do context saving, and to cause interrupt routine forcing or testing. Atomic code, which is defined in this context as a modularized block of code that is executed as a whole without interruption, is achieved because the SWI sets the I bit in the condition code register upon vectoring to the SWI service routine. Here a critical code area can be located that will execute completely before returning to the interrupted module.

If it is desirable to preserve the content of the registers before executing a block of code, then it may be easier to do this by using the SWI instead of calling a subroutine. In a subroutine, the A and X registers can be saved by storing them in variable locations in RAM, but there is no direct mechanism (without doing a bunch of bit testing) to save the condition code register. Instead, issuing an SWI automatically saves the context to the stack. Upon return (RTI) from this interrupt, all registers including the condition code register are restored.

Note about the 68HC08: In the 68HC08 there is an easy means of saving the condition code register by using the TPA instruction followed by PSHA. In fact, all of the registers could be preserved by pushing them onto the stack, but the SWI instruction does this automatically with a small exception. If using the SWI instruction or any other interrupt, it should be remembered that the H register is not preserved automatically. One must use PSHH at the beginning of the interrupt routine and PULH at the end to maintain the register's previous value.

Use of the SWI to save the context while executing a block of code can only be implemented for a single routine unless some selection method is used, such as passing a value (i.e., loaded into the accumulator) to the interrupt routine where a conditional branch can select the correct code to execute. Also note that using the C bit in the condition code register as a Boolean return value, as one might do in a normal subroutine, would not work for an interrupt routine as the condition code register is restored upon return from interrupt to its previous state when the interrupt occurred.

Another use of the SWI involves forcing the execution of another interrupt service routine. This can be especially useful during code testing when it is inconvenient to wait for a real interrupt to cause the execution of its service routine, or if there is a need to test the possible adverse effect of an interrupt during execution of critical code. By assigning the same vector for the SWI as the interrupt whose service routine is to be tested, the SWI instruction can be placed at any point in the program. This same method of forcing execution of an interrupt service routine may be useful in applications where a function needs to be executed both upon the occurrence of an interrupt as well as during normal program flow. Using the SWI to trigger its execution during normal program flow eliminates the need to maintain duplicate code.

Motorola provides TQPACK adapters (specific to each package type) to be surface mounted to your target system, using approximately the same footprint as the chip package. The TQPACK has a number of pins on the top which interface to a TQSOCKET with guides. The TQSOCKET protects the fragile pins (it is not easy removing a soldered TQPACK!) and can be easily replaced if pin damage occurs. A target head adapter, which is specific to the device or family you are emulating, attaches to the TQSOCKET on one end, and to a controlled impedance flexible cable on the other end. The other end of the flex-cable attaches to the emulator system.

The specific part numbers for the MCU you are emulating can be found in our on-line development tool selector guide (SG173/D). Note that the purchase of a QFP target head adapter includes one TQPACK and one TQSOCKET. Additional TQPACKs and TQSOCKETs can be purchased for connecting with more than one target system. You can find the part numbers for additional TQPACKs and TQSOCKETs in the surface mount column of the selector guide. Refer to the following (a picture is worth a thousand words!):

View the addressing mode matrix.

Do not set the SEC bit ($0100 bit 0) while emulating. Setting this bit prevents access to test mode. As the EM board uses test mode, this will cause the device to stop functioning.

Once the SEC bit has been set, it may be cleared by entering the serial bootloader mode with a PGMR board or by UV erasing the part if it has a window. UV erasing will erase both EPROM and EEPROM, thus clearing the SEC bit to the erase state.

The differences are listed in this table:

The CONFIG1 and CONFIG2 registers are write-once registers, and can be changed only once after each reset. Do not use consecutive BSET or BCLR instructions on these registers, as only the first such instruction will cause a change. The values should be written once to each of these registers with an immediate addressing MOV instruction.

Latchup is the breakdown of parasitic bipolar transitors within the MOS device. It results in shorting V_DD to V_SS, which can cause chip self-destruction or at least the requirement to power down and then power back up. Latchup is most likely to occur in I/O devices, where large currents flow, when the voltage on the pin is taken out of spec.

In an n channel CMOS device, one of the bipolar transistors (a pnp) sets up with its base in the n-substrate, connecting the p-type source of V_DD to the p-well. The other bipolar transitor (a npn) is aligned with its base in the p-well and connects the n-substrate to the n-source of V_SS. There is a substrate resistance, Rs, and a p-well resistance, Rw.

In the case of the npn transistor, current will flow from the collector to the emitter if the collector is biased positive with respect to the emitter and the base is about 0.6 V more positive than the emitter.

The pnp transistor conducts from emitter to collector if the emitter is biased more positively than the collector and the base is about 0.6 V more positive than the emitter.

If the current injected into the n-substrate and collected by the p-well is high enough, the voltage drop across Rs can rise to the point where the two bipolar transistors turn on and operate in a low resistance mode. Under this circumstance, the V_DD to V_SS path can become shorted out and cause circuit failure.

Most of what can be done to prevent latchup is done during the design and lay out of the microcontroller itself. Operating the microcontroller within its specification is the best way a board level designer can avoid latchup.

Symptoms:

• High I_DD values
• Part heats up noticeably

Latchup is self-perpetuating once it is started, so its symptoms may be there after the cause of it is gone. The way to stop the latchup process is to remove the power from the chip.

Debugging:
Latchup is almost always the result of pulling a pin above V_DD or below V_SS, so check all pins for this.

Also, be warned that this could be the result of glitches on the pins, so finding the source could require a very tedious debugging session. One way to find an offending pin is to disconnect all inputs and step through trying them either high or low one at a time and then cycle the power and test for when the latchup condition occurs.

Programs written for the 68HC705C8 can be transferred to the 68HC705C8A, provided two locations $FF0 and $1FF1 are programmed with $00.

It is highly recommended that users refer to Motorola application note AN1226/D before using the 68HC705C8A.

Programming the 68HC705C8A
The 68HC705C8A can be programmed with the MC68HC05PGMR-2 and compatibility with the 68HC705C8 can be maintained if the EPROM 2764/27128/27256 location $1FF0 and $1FF1 are programmed with $00. Note that the default value of the unprogrammed locations may be different on different types of EPROMs.

The following discussion will refer to the programmer board MC68HC05PGMR-2.

Programmer Settings
The parallel mode settings are as follows:

Programming Module Preparation
The PGMR must be prepared/configured prior to any program/verify operations. Board preparation consists of external power source (+5 V and V_PP), EPROM installation, DIP PGMR configuration and PLCC PGMR configuration.

External Power Source
Power connector P1 is used to connect an external power supply to the PGMR. A +5 V @ 100 mA power source is connected to connector P1 pins labeled +5V and GND. The programming voltage power source is connected to pins labeled V_PP and GND. Refer to the 68HC705C8A data sheet for programming voltage (V_PP) specifications.

NOTE: The programming voltage (V_PP = 14.5 V to 15 V) must be measured at SKT2 pin 3 during the programming cycle (D6 PROGRAM LED illuminated).

EPROM Installation
The basic EPROM device used on the PGMR (at location U2) is a 2764, 8 K EPROM, 28-pin device. This EPROM device contained the user code to be programmed into the 68HC705C8A.

Programming Operation
To program the 68HC705C8A MCU, perform the following steps:

1. Place switch S1 to POWER-OFF (right position).
2. Install MCU and EPROM devices into the PGMR. If a PLCC MCU is being programmed, it must be inserted into the programming socket (SKT3) upside down (i.e. dead bug).
3. Place switch S2 to RESET-IN (left) position.
4. Select appropriate settings for S3 and JP1-JP5 (as described earlier).
5. Place switch S1 to POWER-ON (left position).
6. Place switch S2 to RESET-OUT (right position). PROGRAM LED illuminates, signifying programming sequence is being performed. VERIFY LED illuminates signifying verification is completed.
7. Place switch S2 to RESET-IN (left position).
8. Remove power (via S1), or select a new routine.

The 68HC(7)05C9A is an enhanced version of the 68HC(7)05C9. In addition to being shrunk to a more advanced process technology, this device offers the following attributes not available on the 68HC(7)05C9:

• Keyboard Scan
  • Each of the eight Port B pins has a mask option to enable external interrupt capability with an internal pull up device.
  • If these mask options are not selected, Port B performance is equivalent to the 68HC05C9.
  • When converting existing C9 patterns to C9A, the Port B mask options are not selected.
• High Current Pin. Port C7 has the capability to sink (10 mA) or source (5 mA) higher current levels than the 05C9 when the pin is configured as an output.
• ROM Security Feature - This logic helps prevent unauthorized dumping of the user's code from the on-chip ROM. The OTP/EPROM versions of C9 and C9A both have a security feature.

The 68HC705P6A is a pin compatible upgrade of the 68HC705P9 with the following enhancements:

• RAM memory increased from 128 bytes to 176 bytes
• EPROM/OTP memory increased from 2,104 bytes to 4,672 bytes
• EPROM/OTP secure mode added
• Keyboard interrupts and pull up options for port A lines
• Two high-current drive pins added (PC0 and PC1)
• Option to treat STOP instruction as a HALT
• Option to program SIOP master clock rate at F_OSC/64, F_OSC/32, F_OSC/16 as well as the 68HC705P9s fixed F_OSC/8

The 68HC705P9 mask option register (MOR) is located at $0900 and is used to control the following options:

• COP enabled or disabled (bit 0)
• IRQ edge or edge and level sensitive (bit 1)
• SIOP Least significant bit or most significant bit sent first (bit 2)

The 68HC705P6A uses address $0900 for EPROM/OTP program area. Two new mask option registers are used on the 68HC705P6A:

• $1EFF controls whether port pull ups/interrupt capability is enabled for each of the port A i/o lines (program $1EFF to all zeros to disable pull ups/interrupts as in 68HC705P9).
• $1F00 controls the following options:
  • COP enabled or disabled (bit 0)
  • IRQ edge or edge and level sensitive (bit 1)
  • SIOP least significant bit or most significant bit sent first (bit 2)
  • SIOP clock rate (new bits 3 and 4, set both for F_OSC/8 as in 68HC705P9)
  • STOP instruction enabled or convert to HALT (new bit 5, clear to enable STOP as in 68HC705P9)
  • EPROM Security Option (new bit 7, clear to disable security as in 68HC705P9)

Carefully review all options selectable by the new MORs and the memory map before using 68HC705P9 code in a 68HC705P6A.

Motorola's M68HC705P9PGMR programs 68HC705P6As without modification, using the same V_PP and following the same procedure as programming 68HC705P9s. If you are using a third party programmer make sure you contact the manufacturer for a possible software upgrade to support programming 68HC705P6As.

The 68HC705P6A is a pin compatible upgrade of the 68HC705P6 with these differences:

• EPROM/OTP secure mode added (selectable by new bit 7 in MOR at $1F00)
• Keyboard interrupts and pull up options for port A lines (selectable by new MOR at $1EFF)
• Two hi-current drive pins added (PC0 and PC1)
• No MPGM (Mask Option Programming) bit at address $1C, the EPROM Programming Register

Carefully review all options selectable by the new MOR before using 68HC705P6 code in a 68HC705P6A. To configure a 68HC705P6A to operate like a 68HC705P6 without any enhancements, make sure the MOR at $1EFF is programmed to all 0s (disable pull ups/interrupts on port A) and that bit 7 of the MOR at $1F00 is programmed to 0 (disable secure mode).

Motorola's M68HC705P9PGMR programs 68HC705P6As without modification, using the same V_PP and following the same procedure as programming 68HC705P6s. If you are using a third party programmer, make sure you contact the manufacturer for a possible software upgrade to support programming 68HC705P6As.

The 68HC705C9A can be set up to emulate either an 68HC05C9A or an 68HC05C12A. This table highlights the capabilities and features of each mode of operation.
 

The A strategy was introduced to enhance the features that the device offers, including:

• Port A pull ups
• High current drive on PC0 and PC1 (EP)ROM security

The V_PP1 pin of the B6 is a very high impedance pin that is normally not used by the customers application. This pin is used by the tester in the factory. The high impedance can cause problems with some applications. Very high humidity or very noisy environments may cause programming problems so the following is a quick look at what to do with V_PP1.

If the application does not write to or erase the EEPROM1 array during normal use, connect the V_PP1 pin to V_DD.This will ensure that no noise will influence the EEPROM circuit.

If the application does write to or erase the EEPROM1 array during normal use, shield this pin as much as possible. Use plenty of GND track nearby. Some customers have placed a small capacitor (1 nF) to decouple the V_PP1 pin. This should not affect the programming in normal use (10 mS programming time) despite slightly lengthening the rise time of V_PP1.

View the C Family Matrix.

After requesting the MCAN sleep mode, the CPU usually checks if the sleep state really was entered. The MC68HC05X16 and the MC68HC(7)05X32 microcontrollers offer a sleep flag, which acknowledges the sleep request. This MCAN asleep flag (CAF) is located at bit 6 of the EEPROM/ECLK control register. The MC68HC(7)05X4 microcontroller also offers such a sleep mirror bit, which is located at bit 3 of the port configuration register (SLEEP).

After a successful sleep request, which is indicated by a set sleep flag, a STOP instruction may be entered to power down the CPU. If the sleep flag is not set, a new message may be arrived, which can activate a receive interrupt in case of a valid, accepted message. After a certain waiting time, the CPU could try again to enter sleep mode.

The oscillator clock will stop only if the STOP instruction is executed after the sleep request. Otherwise, only the clock path of the MCAN module is stopped.

There are several reasons why the MCAN module could not enter sleep mode after setting the sleep request bit:

• The sleep request has been activated during message reception or transmission, which immediately causes a wakeup interrupt. Before setting the sleep request bit, always verify that no transmission is pending and that the MCAN module is in idle mode.
• The sleep request has been entered immediately after the CAN initialization routine. Perhaps not enough time elapsed between clearing the MCAN reset request and the sleep request so that the MCAN module could not re-enter normal operation mode. To wait for the occurrence of 11 consecutive recessive bits on the bus, a small wait loop should be included after clearing the reset request bit. Then the MCAN module starts normal operation and sleep can be requested. (For more details, see How are the MCAN module registers initialized?)
• The CCOM register has been used wrongly. A read-modify-write operation such as BSET may be used to set the sleep bit. This register is write only and returns the value $FF when reading it. Thus, a BSET instruction would first read $FF, then set a bit and write $FF back to the CCOM register, which would result in a non-functional CAN module. LDA/STA instructions should be used instead to set a bit.
• One-line mode was selected, but the comparator selection bit, COMPSEL, of the CCOM register was set. In one-line mode, COMPSEL should be cleared. (For more details, see When should and how should the single-line mode be used?)

Error management can be defined for the lowest level of the OSI reference model, but also for the higher communication levels of this reference model. Only the low-level error management is discussed here.

The definition of the error management depends very much on the intelligence of the physical interface. When using a transceiver with integrated automatic single-line switch, the software for bus error handling gets reduced. In case of an active error, there's no need for a two-line/one-line mode switch by the software, as this is done in hardware by the transceiver itself. Within the error interrupt routine, the status line of the transceiver, which reports failure mode, could be evaluated and reported to the CAN management software.

When using a simple bus transceiver, no function in the physical interface device recognizes a short circuit or interruption of a bus line. Usually the error management software with this type of transceiver just tells the management software that a bus failure has occurred. Extra, costly hardware would be needed for bus failure sensing.

Another possible implementation is a discrete physical interface, where the two-line mode of the MCAN is used. With this configuration, an active error status could trigger a software algorithm within the MCAN interrupt routine to detect a faulty bus line.

Error status:
The error status bit is set when the receive or transmit error counter reaches value 96. The MCAN interrupt handler should give an indication to the CAN management software that the bus may be heavily disturbed. To avoid a resultant bus off state (only produced by transmission), this may lead the management software to stop any further transmission, if possible.

When using the two-line mode with a discrete physical layer, the error status interrupt software could trigger an algorithm to detect possible bus line interruption or short circuits.

Bus off status:
When the bus status flag in the status register CSTAT gets set, a bus off condition is signaled, which means the internal transmit error counter reached the value 255. This state can never be reached, if the node is in receive mode or if there is only one node on the bus. Within the MCAN interrupt routine, the RR bit should be cleared and the management software should be made aware of a problem on the bus.

NOTE:
The error status and bus off bits are level sensitive. But the error interrupt flag is not level sensitive. The interrupt flag gets set only when either bus off or error status bits change. If the error interrupt becomes active due to a set error status bit, the error interrupt flag gets set and will call the MCAN interrupt handler, when the error interrupt has been enabled. After clearing the error interrupt flag within the MCAN interrupt routine, it gets set again only if the bus off state gets active in addition to error status or if error status was cleared and then set again.

The following phenomenon has to be considered when resynchronization on both edges is selected. In that mode, a transmitter will resysnchronize on positive phase shifts if a dominant bit is sent. If the transceiver delay of that node is larger than the SYNC time quanta, the transmitting node receives its sent bit edge after the SYNC time quanta and then resynchronizes itself. This will result in a variable bit time/baud rate on the bus. In a CAN network with a different bit timing definition in some CAN nodes (for instance, due to different used crystals), this could cause bus failures.

As described earlier, an enhanced CAN protocol was added, which allows phase shifts of a whole bit time after long sequences of equal bits. With these modifications to the original CAN protocol, the resynchronization on recessive-to-dominant edges as well as dominant-to-recessive edges has absolutely no advantage over resynchronization on recessive-to-dominant edges only. The oscillator tolerance is the same for both ways of resynchronization.

Therefore, resynchronization is recommended only on recessive-to-dominant edges.

In some cases, an urgent message gets activated, for example, by the network management software, but the transmit buffer is full. Then the loaded message has to be aborted to release the transmit buffer for the new message.

First the abort transmission bit (AT) in the CAN command register (CCOM) has to be set to request the abortion of a pending transmission. If the transmission is not already in progress, the buffer is released immediately, which sets the transmit buffer access bit. In the case of an enabled transmit interrupt, the transmit interrupt request gets asserted, which allows an orthogonal interrupt handler. Within the transmit interrupt routine the new message then will be copied automatically into the transmit buffer and requested for transmission.

If the transmission already is in progress when an abort request is being received, the abort request remains active and will be evaluated in the next interframe space. In case of lost arbitration on the bus, the abortion of the old message could then be executed as described above. In that case, the transmit buffer would not get released immediately after the abort request, which has to be considered in polling mode when no transmit interrupt is used. The transmit buffer access bit (TBA) in the CAN status register should be polled to indicate the released state before writing the new message into the buffer. Otherwise, the new data get lost without being signaled.

When programming the 68HC705K1 on the KICS board, the user types PROGRAM in the DEBUG window. After a couple of instructions of manipulating the hardware, the Programmer Menu pops up. Some users may think that if they select the 'P' option, all of the EPROM memory locations will be programmed. This is incorrect. Only the bulk user EPROM array is programmed. The Personality EPROM and the MOR byte are NOT programmed. You have to program these bytes separately using the 'E' and the 'M' options.

As described, the MCAN module offers two receive buffers which can be accessed by the CPU or the CAN bus. Both buffers alternate with each other to receive data from the bus. This gives the CPU time to read a message buffer while a new message is being received at the same time. The illustrations demonstrate the steps involved during a message reception.


1. Both receive buffers were empty and released to allow reuse by the CAN interface. A new message arrives and will be written into receive buffer 1.

Receive status (RS): 1
Receive buffer status (RBS): 0
Receive interrupt flag (RIF): 0
Release receive buffer (RRB): 0

Receive status (RS): 0
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 1
Release receive buffer (RRB): 0

Receive status (RS): 1
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 0
Release receive buffer (RRB): 0

Receive status (RS): 1
Receive Buffer status (RBS): 0
Receive Interrupt Flag (RIF): 0
Release Receive Buffer (RRB): 1

Receive status (RS): 0
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 1
Release receive buffer (RRB): 1

Most applications today implement an integrated physical bus interface device which is specified for a higher drive current and which includes short-circuit protection and slope control. Some newer interface circuits even integrate an automatic single-wire mode switch, which recognizes an interrupted or short-circuited bus line to GND/ V_DD and automatically switches to one functional bus line.

The appropriate physical interface for a system depends on the speed, which is needed for the CAN bus. There are low-speed physical interfaces (<125 kBaud) and high-speed physical interfaces (up to 1 Mbaud).

When using external transceiver devices, the internal comparator logic of the M68HC05 Family is not needed. Only one transmit and one receive line are connected between the microcontroller and the transceiver. The voltage reference pin, V_DDH, of the X-microcontroller can be left open, if internally the V_DDH reference is connected to one comparator input. This can be done by initializing the CCOM and COCNTRL register for single-line mode. (For more details, see When should and how should the single-line mode be used?)

Two examples of the 68HC05X controller combined with an external transceiver are shown here. When using a Philips PCA82C250, only three pins need to be connected. Use one TX and one RX CAN line (either 0 or 1 can be chosen) in addition to one input/output pin, which controls the output slope of the bus signal and the standby mode of the transceiver. If the port pin is set to low, the output slope will be controlled via the current through the resistor. This is used in applications with lower CAN bus speed. By switching the port pin to high, the transceiver enters the low-power mode because no current passes through the pin.

The second example shows the use of the newer, more sophisticated, low-speed transceiver PCA82C252 or SN65LBC032. This device is connected to VBAT to detect a short circuit to the battery and ground. In case of bus failures, the device automatically switches to single-line mode, which reduces the 68HC05X microcontroller's error handling software.

In addition to the CAN lines TX and RX, three input/output pins and one interrupt/wired or interrupt pin have to be spent to control the transceiver. The connections to EN and NSTB control the mode of operation of the transceiver (sleep, standby), and the input/output line to NWKUP can enable a wakeup request to the powered down transceiver. Feedback of any failure on the bus or of a wakeup is sent to the microcontroller via the NERR line, which triggers an interrupt.

Under certain conditions, the RESET pin will be pulled low by internal circuitry. This indicates some internal error condition. The 68HC705C8A RESET pin will be pulled low by three internal conditions:

• The clock monitor reset (if enabled)
• The programmable COP reset (if enabled)
• A power-on reset

The 68HC705C8A RESET pin will not be pulled low by a reset caused by the non-programmable COP. This behavior is consistent with the C4A MCU (which had the non-programmable COP).

To define bit time and the length of its time segments, some rules have to be followed. The CAN specification defines a bit time consisting of four segments. These segments are:

Synchronization segment (SYNC)
Propagation segment (PROP)
Phase segment 1 (PS1)
Phase segment 2 (PS2)

Length of Time Segments
SYNC = 1 Tq
PROP = 1,....,8 Tq
PS1 = 1,....,8 Tq
PS2 = max(PS1,2)
SJW = 1, ... min(4, PS1)
with fN = Synchronization Jump Width

Requirement 1:
Sample correctly the first bit after sending an active error flag (localizing bus errors)

(2 * df) * (13 * BT - PS2) < min (PS1 ,PS2)

Requirement 2:
Correct synchronization in stuffed part of the bit stream

(2 * df) * 10 * BT < SJW

with fN = nominal CAN clock frequency
f = actual CAN clock frequency
df = relative clock difference: (df = | f - fN | / fN)

CAN bus frequency 500 Kbaud ... 2 us bit time
Bus driver delay 50 ns
Receiver circuit delay 30 ns
Bus line delay (40 m) 220 ns
Total propagation delay 600ns

Oscillator frequency 16 MHz

Tq = tscl = (2 * P)/ F_OSC = 125 ns

Time quanta per bit time 16 Tq
Prescaler 1

Propagation delay segment 5 Tq = 625 ns

Phase segment 1 5 Tq
Phase segment 2 5 Tq

TSEG1 (PROP + PS1) 5 Tq + 5 Tq = 10 Tq
TSEG2 (PS2) 5 Tq
SJW 4 Tq

For the MMDS:

• Make sure the revision of the MMDS mother board is at least assembly F, revision 5 (change made in October 1994). If you have an older revision, contact Global Data Specialists in North America for information on how to upgrade the MMDS to current revision. They can be reached at (800) 451-3464 or (602) 437-4331. For all other regions, please contact your local Motorola sales office or authorized distributor.

• Download the new MMDS host software for the 68HC08 (mmds08.zip).

• Download the updated MMDS Operations Manual (MMDS0508OM/D).
• Purchase the device-specific 68HC08 emulation module

For the MMEVS:

• The MMEVS is fully compatible with device specific 68HC08 emulation modules.

For the EVS:

• The EVS cannot emulate at the high bus speed of the 68HC08. Users will need to upgrade to the MMEVS for 68HC08 emulation.

The MCAN registers usually are initialized within a separate CAN initialization routine. For some registers, it is mandatory to be in the CAN reset state during initialization, which is entered by setting the reset request bit in the CAN control register.

These registers are:

Acceptance code register (CACC)
Acceptance mask register (CACM)
Bit timing register 0/1 (CBT0, CBT1)
Output control register (COCTRL)

NOTE:
The CAN command register (CCOM) must not be modified by using the read-modify-write instructions BSET/BCLR. This register is write only and returns the value $FF when reading it. Thus, a BSET instruction would first read $FF, then set a bit and write $FF back to the CCOM register, which would result in a non-functional CAN module.

When setting the MCAN out of reset mode (clearing RR bit), remember that the MCAN module doesn't start normal operation immediately. In a normal situation, MCAN waits for 11 consecutive recessive bits on the CAN bus before starting normal operation. If the bus off state is active, MCAN waits for 128 occurrences of 11 recessive bits before starting normal operation.

Therefore, a wait loop after the reset sequence should be added to make sure that no MCAN action, such as a sleep mode request, is activated before MCAN re-enters normal operation mode.

This diagram shows the usual sequence of a CAN initialization routine.

The init routine usually should be executed only after power-on reset. Therefore, the bus off state does not need to be checked, and there is no need to wait for 128 times 11 consecutive recessive bits within the init routine. Usually, bus off failure is handled separately. (For more details, see How should a bus error or bus off condition be handled?)


Here is an example of an MCAN initialization routine written in assembler language.

An overrun condition occurs if both receive buffers are full and a third message occurs. The following pictures illustrate such an overrun event. In this example, receive and overrun interrupts are enabled. Reading of the message buffers is controlled by the MCAN interrupt routine.

1. In this overrun example, the first received message is ready to be read by the CPU, while a second one is received from the bus and written into receive buffer 0. Due to other peripheral interrupts, such as a timer interrupt, the receive interrupt routine cannot start immediately to readout receive buffer 1.

Receive status (RS): 1
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 1
Release receive buffer (RRB): 0

2. The receive interrupt routine starts and reads the message in receive buffer 1. Receive buffer 0 is now full, and a receive interrupt request for receive buffer 0 will be asserted. A third message arrives, which cannot be written into a buffer since the first message buffer is accessed by the CPU and the second one is full. The new message is dropped. This is indicated by the data overrun status bit (DO), which is set. If data overrun interrupt has been enabled in the MCAN control register, the MCAN interrupt line remains asserted, since it is still asserted by the receive interrupt.

Receive status (RS): 1
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 1
Release receive buffer (RRB): 0
Data overrun (DO): 1

Receive status (RS): 1
Receive buffer status (RBS): 1
Receive interrupt flag (RIF): 0
Release receive buffer (RRB): 0
Data overrun (DO): 1

Within the active MCAN interrupt routine, all MCAN interrupt flags have to be checked to start the corresponding interrupt subroutines. In this case, both the receive and the data overrun interrupt subroutines will be executed.

Within the data overrun subroutine the only action is to clear the data overrun status bit by setting the clear overun status bit COS in the CCOM register.

The MCAN module's message buffers are implemented as a BasicCAN structure. Three buffers are implemented in RAM - one transmit buffer and two receive buffers - and each is accessible by either the CPU or the CAN bus at the same time. Because the module has two receive buffers, its software can read a received message while another message is being received from the CAN bus. (Refer to How does the Ping-Pong principle of the two receive buffers work?) A BasicCAN structure offers the advantage of having no fixed link between a receive buffer and a message identifier. Instead, a programmable 11-bit identifier filter defines which messages are allowed to be received.

The usual CAN configuration uses two signal lines which transmit a differential signal. A differential signal allows redundancy so that the system is less sensitive to bus failures in a disturbed environment. The transmitter and receiver of the MCAN module also can be set in a single-line mode, where only one line is used to transmit the signal. This mode could be used due to these reasons:

• The MCAN uses an external bus transceiver, which generates the differential signal itself.
• The environment is less critical, so that the system can renounce the redundancy of the 2-line mode.
• Due to short circuit to ground or battery of one bus line or due to an interrupted bus line, the communication fails (error status active). One communication line is still operational.

One-line communication mode on the receiver side is entered by connecting one input of the internal receive comparator to a fixed reference voltage. The internal 2.5-V (V_DDH) reference should be used to save additional external connections. The switch to V_DDH is done in the CCOM register. Three bits have to be taken care of to use 1-line mode: RX0, RX1, and COMPSEL.

On the transmitter side, only one transmit line should be enabled in single-line mode. The unused transmit line should be set into a floating state. This is set up by the appropriate value in the output control register.

The following pictures show the physical schematics of the MCAN physical interface in one-line mode (RX0/TX0 active) and the required register settings which have to be chosen in one-line mode:

One-line mode on TX0/RX0 line:

One-line mode on TX1/RX1 line:

The TX line polarity depends on the external physical interface. The register setup shown here uses positive polarity, as an example of the use of an external bus transceiver.

NOTE:

The COMPSEL bit has to be cleared in one-line mode, which means that both main comparator inputs are compared to each other to recognize a wakeup condition on the bus. Since one comparator input remains connected to V_DDH by setting RX0/1, this configuration leads to the comparison of one single bus line with V_DDH (bottom sleep comparator SC in the schematics). If COMPSEL would be set in single-line mode, the two middle comparators would be used for wakeup recognition. In this case, one comparator would compare V_DDH against V_DDH, which is an unpredictable condition. When entering sleep mode this setup could immediately wake up the MCAN module.

NOTE: The CAN command register (CCOM) must not be modified by using the read-modify-write instructions BSET/BCLR. This register is write only and returns the value $FF when reading it. Thus, a BSET instruction would first read $FF, then set a bit and write $FF back to the CCOM register, which would result in a non-functional CAN module.

The oscillator stops only if the CPU executed a stop instruction and the CAN module was set into sleep mode. It remains in stop until either an external interrupt or a CAN interrupt occurs.

The MCAN module has been designed according to CAN protocol 1.2 (standard CAN, 11-bit identifier) as defined by Robert BOSCH GmbH. The two reserved bits, r1 and r0, within the control field are sent as dominant bits and are not evaluated during reception.

Bit r1 of those reserved bits has been redefined within CAN standard 2.0 B (extended CAN, 29-bit identifier). It has been renamed to IDE bit (identifier extension) and distinguishes between extended CAN and standard CAN format.

Because the IDE bit is not evaluated in the MCAN module, an extended, 29-bit identifier frame would be treated as a standard frame, which would lead into a form error.

The following is needed to emulate the 68HC705KJ1:

• Either the MMDS05 emulation station or the MMEVS emulation board
• M68EM05J1A Emulation Module (emulates both the 68HC705J1A and the 68HC705KJ1)
• M68CBL05A Emulation Flex-cable
• M68TA05KJ1P16 Target Head Adapter
• M68DIP16SOIC Surface Mount Adapter (if using the SOIC package)

To program the 68HC705KJ1, we recommend the M68ICS05KJ In-circuit simulator/serial programmer. If you do not already have a MMDS or MMEVS, we recommend the KITMMEVS05KJ or the KITMMDS05KJ. Each of these kits includes everything you need in one easy to order kit.

No collisions occur because the CPU accesses data on the falling edge of a clocked signal and the A/D accesses data on the rising edge of a clocked signal.

Symptom:
A customer has experienced problems when trying to emulate an 68HC05X16 using the M68EML05X32 Emulation Board. The problem has manifested itself in two ways:

1. An unexpected RESET occurs while trying to execute an 'LDA' or 'STA' instruction. This happens as instead of reading the data byte, the low byte of the address is given back - this usually happens when a reserved address gets accessed but was happening when valid addresses were being accessed also.
2. The device jumps to address $7196 - because this address is out of range, the emulator stops.

Explanation:
The symptoms experienced seem to suggest that there is some problem with the memory mapping involved in emulating an 68HC05X16 using the resident device on the M68EML05X32 emulation board (which is an 68HC705X32).

Solution:
The problem was solved by replacing the resident 68HC705X32 device with an 68HC05X16 device.

Root cause fix:
A root cause fix has not yet been found as the severity of the problem is yet to be fully quantified. Only one customer has reported the problem so far.

The boards were layed out to accept an SOIC socket but were not populated to keep the cost of the boards as low as possible. The socket can be ordered from Yamaichi at 408-452-0797 or Emulation Technology at 408-982-0660. The Yamaichi part number for the 16- to 28-lead SOIC socket is IC51-0282-334-1. The Emulation Technology part number is S-SOR-00-028-D.

Any EM compatible with the MMDS can be used in the MMEVS. This includes all EMs that have M68EM05xx part numbers (check the user's manual). A few M68HC05xxEM boards may not work in the MMEVS or MMDS. Attempting to use these older designs in the MMDS or MMEVS will result in an error message concerning an improper identification address. Trying to use an older system will not damage either the system or the EM board.

Find out if your existing EM can be used with the new MMEVS by checking the on-line compatibility table.

The MMEVS and the MMDS utilize configuration files to describe the memory map of the emulating MCU and to provide CHIPINFO. The appropriate configuration/memory file will be needed to use the MMDS or MMEVS. All configuration files are available to download from our EM Config page.

MMEVS and MMDS systems use a modular emulation module (EM) to configure emulation for a particular member of the 68HC05 Family. This modular approach allows each system to be upgraded to support new MCUs at minimal cost. The older non-modular EVMs could not be upgraded. The new modular approach allows each system to be upgraded to support new MCUs at minimal cost. The older non-modular EVMs could not be upgraded. However, the older EVS system allowed some level of upgrading but could not handle low pin count MCUs, large memory MCUs, external bus MCUs, high speed MCUs, or low-voltage MCUs. Current users of EVM and EVS products can continue to utilize these tools for cost-effective emulation/evaluation but may want to upgrade to take advantage of the MMEVS's new capabilities. Motorola recommends that any new purchases should use the MMEVS instead of the EVS.

• Real-time, non-intrusive, in-circuit emulation
  • New support for high-speed 68HC05s (68HSC05)
  • New support for the high-performance 68HC08 Family
  • New support for emulation at low voltages (down to 1.8 V)
• New support for popular MCUs
  • Cost-effective, real-time emulation of 68HC(7)05J1A and 68HC(7)05K series (The EVS cannot emulate small pin count MCUs.)
  • Increased emulation memory to 64 K to handle the largest memory MCUs
  • Emulates external bus MCUs such as the 68HC05C0
• Eliminates the EVS/EVM limitations of using software breakpoints
  • 64 hardware breakpoints vs. five software breakpoints
  • Avoids potential problems when mixing interrupt requests (IRQ) and user software interrupts (SWI)
  • Traces clear interrupt (CLI) and return from interrupt (RTI) instructions while interrupts are pending
  • Uses conditional branch instructions that branch to itself
• Dual microcontrollers for faster command and code transfers
  • Features up to 57600 baud vs. 9600 baud
• Enhanced script and new command logging capability
  • Allows automatic execution of a sequence of MMEVS commands to automate tasks such as configuration setup and repeatable test/diagnostic routines
• True subset of the higher performance MMDS development system
  • Allows greater flexibility in mixing and matching Motorola hardware tools with the ever-increasing variety of C compilers, assemblers, and integrated development environments products offered by Motorola's third party developer companies
• New CHIPINFO command to make obtaining information about the device being emulated easier
  • Memory map, vectors, registers, and pin-out information
• Software-selectable oscillator clock sources
  • Up to six choices to eliminate manually changing the oscillator
• True source-level debugging
• Enhanced on-screen, context-sensitive help via pop-up menus and windows
• Latch-up resistant design makes power-up sequencing unimportant
• Provides automatic detection of user programs that access non-valid memory locations
• Reorganized and reformatted documentation for easier use in both traditional printed format and in searchable, hypertext-linked, on-line format

The standard version, the 68HC705KJ1, is specified to operate at an internal operating frequency of DC to 4.0 MHz @ 5 V and DC to 2.1 MHz @ 3.3 V.

The 68HLC705KJ1 has the same range of operation but it has been optimized to operate more efficiently at low frequencies, in particular at 16 kHz internal operating frequency. Because of the more efficient oscillator circuit at low frequencies, this version provides a power saving over the standard HC version when operating at low frequencies. This saving is more dramatic the slower the device is operated and the lower the supply voltage is.

For example, a recent test found that at 100 kHz internal operating frequency, the HLC version drew about 17% less current at 3.3 V than the HC version operating under the same conditions. Regardless of the version used, care should be taken in selecting external crystal components to minimize power demand while still guaranteeing proper operation under all expected operating conditions.

Note: The 68HLC705KJ1 is not a low-voltage part. It operates at the same voltages as the standard 68HC705KJ1. The reduction in power consumption is achieved through lower operating frequency.

Quiescent Current Values

68HC705V8 Stop Regulator enabled (includes Stop I_DD, LVR disabled) = typical value of 600 uA

68HC05V7

Stop Regulator enabled (includes Stop I_DD, LVR disabled) = typical value of 250 uA

Reasons for Differences:
Design changes to the V7 voltage regulator module reduced the STOP current. Resistors were re-layed out to reduce the current. However, this made the module larger and the 68HC705V8 could not accommodate this without a large issue. Also, the MOR register on the 68HC705V8 draws current as well.

By : Ken Obuszewski

Date :July '98

Remarks:
The current consumption on the 68HC705V8 is dominated by three factors:

1. V_OLtage regulator - (around 350 uA)

2. LVR circuit - (around 100 uA if enabled)
3. Unprogrammed mask options

There were design changes made to the V7 voltage regulator module to reduce the STOP current. Resistors were re-layed out to reduce the current. However, this made the module larger and the 68HC705V8 could not accommodate this without increasing die size, and since the V7 was meant to be the production device, it was not a large issue. Also, the MOR register on the 68HC705V8 draws current as well.

If not using the full 4 * 16 segment driving capability of the L1 device it is possible to incur a high run I_DD current due to the segment display pins being left unconnected. In order to avoid this it is necessary to connect the unused LCD pins to ground.

The following are preliminary estimates of the 68HC705B32 power consumption. When the device is fully characterized a rev 5 of the data book will be published with final values.

Supply Current for 5 V Operation (page H23)

RUN (SM=0) IDD TYP = 3.6	MAX = 6 mA
RUN (SM=1)	IDD TYP = 0.9	MAX = 3 mA
WAIT (SM=0)	IDD TYP = 1.1	MAX = 2 mA
WAIT (SM=1)	IDD TYP = 0.7	MAX = 1.8 mA
STOP 0-70	IDD TYP = 10	MAX = 20 uA
-40 to 85 IDD	TYP = 10	MAX = 20 uA

Supply Current for 3.3 V Operation (page H24)

RUN (SM=0)	IDD TYP = 1.3	MAX = 3 mA
RUN (SM=1)	IDD TYP = 1	MAX = 2.8 mA
WAIT (SM=0)	IDD TYP = 0.8	MAX = 1.5 mA
WAIT (SM=1)	IDD TYP = 0.5	MAX = 1.5 mA
STOP 0-70	IDD TYP = 10	MAX = 20 uA
-40 to 85	IDD TYP = 10	MAX = 20 uA

The treatment of unused I/O pins may vary with an application's cost, environmental, and noise requirements.

Because 68HC05 and 68HC08 MCUs are CMOS devices, unused input pins should be terminated to ensure proper operation and reliability. If an input pin is left floating, it can cause oscillation, noise, and excessive current consumption.

The best method to terminate unused inputs is with a pull up or pull down resistor for each unused pin. Sometimes input-only pins are connected to each other, through a common termination point and resistor. Although this is an inexpensive solution, it is much harder to use one of these pins if needed later. Inputs can be connected directly to V_DD or V_SS, however this makes it more difficult to change the level at that input. If a resistor is used to pull up or pull down the input, then a signal can be connected more easily at a later time.

Unused input/output (bidirectional) pins may be connected to V_DD or V_SS through a resistor for each individual pin. ins configurable as outputs should not be connected directly to V_DD or V_SS.

Some applications leave these pins unconnected and reconfigure them as outputs (through software) during initialization. This can be adequate for higher speed applications involving clock sources with fast startup times. There is still a brief period during reset and initialization where these pins are unterminated inputs. There is also the possibility of a malfunctioning MCU failing to properly switch these pins to outputs.

The liberal use of pull up/pull-down resistors can reduce both current consumption and the possibility of electrostatic damage. The use of individual resistors for each pin can make future expansion and reconfiguration easier.

To clarify the biasing schemes:

We have currently the following mask sets

G91G is the Puck
G45V is the Puck2
H81A is the Kobold 805
J47D is Kobold2 805

From a software point of view, J47D and H81A are identical. G91G and G45V both differ from H81A and J47D.

The Specification Rev1.2 and Rev 1,3 cover the H81A/J47D silicon.

The Bit 3 in the MFtest register control the following on the J47D:

• The relay drivers are no longer biased by setting (PC5/6)
• When set and the HTR mask option is not set, the temperature sensor is also no longer biased
• There is no effect to PC4 Biasing of the inputs on PC0 .. PC4 is deselected by setting Bit7 of the MFTEST register.

Most likely, the emulator has got G45V (Puck2, Rev0.9 of the spec is valid.

By setting the Bit3 of the MFtest register, PC5 and PC6 outputs, temperature sensor and PC0. PC4 inputs are de-biased and non-functional. PC4 output is not affected.

If the emulator has got G91G (Puck1) silicon, suggest replace it with H81A or J47D silicon, since the PC0. PC6 output structure is very different as is the biasing scheme.

To clarify the biasing schemes:

We have currently the following mask sets

G91G is the Puck
G45V is the Puck2
H81A is the Kobold 805
J47D is Kobold2 805

From a software point of view, J47D and H81A are identical. G91G and G45V both differ from H81A and J47D.

The Specification Rev1.2 and Rev 1,3 cover the H81A/J47D silicon.

The Bit 3 in the MFtest register control the following on the J47D:

• The relay drivers are no longer biased by setting (PC5/6)
• When set and the HTR mask option is not set, the temperature sensor is also no longer biased
• There is no effect to PC4 Biasing of the inputs on PC0 .. PC4 is deselected by setting Bit7 of the MFTEST register.

Most likely, the emulator has got G45V (Puck2, Rev0.9 of the spec is valid.

By setting the Bit3 of the MFtest register, PC5 and PC6 outputs, temperature sensor and PC0. PC4 inputs are de-biased and non-functional. PC4 output is not affected.

If the emulator has got G91G (Puck1) silicon, suggest replace it with H81A or J47D silicon, since the PC0. PC6 output structure is very different as is the biasing scheme.

Each bidirectional (input and output) port has its own data direction register. These addresses typically come immediately after the locations of the data registers. In the 68HC705C8A, the data direction registers are at $0004, $0005, and $0006 for port A, B, and C, respectively. Port D on the 68HC705C8A is an input-only port. Therefore, it does not have a data direction register.

The bits in a port's data direction register reflect the direction (input or output) of its pins. A value of 0 in a data direction register configures a port pin as an input. A value of 1 configures a pin as an output. On reset, bidirectional port pins are configured as inputs, as bits in the data direction register are cleared on reset.

IMPORTANT:
To avoid a glitch on the output pins, write data to the I/O Port Data register before configuring it as an output. This will ensure the desired output level at the pin when it is switched to an output.

Yes, program PA 1,2,3,6,7 as inputs via DDRA, program PA 0,4,5 as outputs via DDRA and select PA1 as analog input via ADSCR

Yes, program PA 1,2,3,6,7 as inputs via DDRA, program PA 0,4,5 as outputs via DDRA and select PA1 as analog input via ADSCR

Port C0 to C4 can be configured as inputs. Port C5 and C6 are open-drain outputs only.

Port C0 to C4 can be configured as inputs. Port C5 and C6 are open-drain outputs only.

The two important conditions to guard against are operating outside of specified maximum or minimum voltages and currents. One should take every step necessary to ensure that the voltages at an I/O pin stay within the specified ranges.

If the possibility exists of an input exceeding voltage limits (i.e., below V_SS or above V_DD), a current-limiting device (resistor) should be considered. Internal diodes will latch the input voltage to a diode drop above V_DD or below V_SS. At that point, there is nothing internally which considered. Internal diodes will latch the input voltage to a diode drop above V_DD or below V_SS. At that point, nothing internally will limit current flow. The user should ensure that voltages at an input remain within the recommended range.

Zap refers to damage caused by very high-voltage static electricity exposure. Be careful during handling and assembly of MCUs, to avoid exposing the part to such voltages.

Latchup refers to the unintentional activation of parasitic transistors. This can occur with the application of voltages above V_DD, or below V_SS. Be careful to avoid exposing I/O pins to voltages or currents which exceed those stated in the electrical specification.

For the electrical specifications of an I/O pin, consult the part's Technical Data Book or General Release Specification.

Look at the DC Electrical Characteristics table for the corresponding operating voltage (V_DD). The headings "Output High V_OLtage" and "Output Low V_OLtage" show the maximum current loads which guarantee proper operation.

This table is taken from the MC68HC705KJ1 Technical Data book. The specification for Iload in the Output High V_OLtage category is the guaranteed current source capability at the specified V_OH. Likewise, the Iload in the Output Low V_OLtage category is the guaranteed current sink capability at the specified V_OL. Many of our data books also show the typical port characteristics across different V_OH and V_OL.

The 68HC705KJ1 MCU has LED drive capability on all port pins. LED drive is provided by allowing a pin to sink a typical LED current (~10 mA). This is reflected in the Output Low V_OLtage (sinking current) specification. The table shows that each Port A pin can sink up to 10.0 mA. Under the Output High V_OLtage category, we see that PA4-PA7 can source 2.5 mA at a V_OH of 0.8 V, while the other port pins can source 5.5 mA at the same V_OH.

IMPORTANT:
There is a significant difference between the maximum ratings for current and voltage, and operating current and voltage. The "Maximum Ratings" tables show the limits to which the MCU can be exposed without permanently damaging it. If a part is exposed to the maximum ratings, it is not guaranteed to operate properly. For example, the 68HC705KJ1 specifies a maximum of 25 mA per pin. Operating at that current may affect long-term reliability through metal migration. For long-term reliability, Motorola recommends following the specified Iload vs. V_OH and V_OL.

The direction of the port pin, determined by the data direction register, decides whether an action involves the data latch or the actual pin.

In input mode, a read returns the status of the port pin. If a pin is configured as an input, and a write is made to the corresponding bit in the data register, then the data is written to the output buffer (data latch) without affecting the pin value.

If a pin is configured as an output, a read will return the value in the output buffer.

The following table summarizes the result of read/write actions on input/output port pins. The chart assumes a bidirectional port pin.

* R/W is an internal signal.

Depending on the part, I/O pins can have many different features. Here are some of the various characteristics of I/O pins:

Data Direction
Some pins are bidirectional, while others are input only or output only.

External Interrupt Capability
Certain parts have I/O pins which can be programmed to generate external interrupts. On some parts, these ports are connected directly to the external interrupt line, ORing themselves with the IRQ input. On other parts, the pins are used as a KWI (keyboard wakeup interrupt) for keyboard input. Some provide a second (IRQ2), independent interrupt source.

High Current Sink/Source
Some MCUs have pins which can sink more current than others. This provides the capability to drive LEDs or other similar loads. Some pins can both source and sink extra current.

Alternative Outputs
The output pins of some MCUs can be driven by alternate sources. For example, the 68HC705B16 MCU can output the internal CPU clock to one of its port pins. The 68HC705JP7 has a pin which can be driven by the output of an internal voltage comparator.

Shared Functions
Many of the MCU port pins are shared with other MCU subsystems such as serial interfaces, A/D converters, or timer functions.

From a programming perspective, an I/O port is made of several components. Each port has a data register, represented by a memory address. In M68HC05 and M68HC08 devices, these are typically the first locations in memory. For example, the 68HC705C8A has four I/O ports: A, B, C, and D with four memory addresses. These are located at $0000, $0001, $0002, and $0003, respectively.

If a port pin is configured as an output, a write to its data register bit is placed in the output buffer and is transferred to the pin. If configured as an input, a read from a data register location will return the current value of the pin.

In parts which have this capability, there are typically three considerations to allow an interrupt from an I/O port:

1. The corresponding pull up enable bit and/or interrupt enable bit for the port pin should be set. This varies from part to part. Usually this is through a MOR (mask option register) or some other configuration register.
2. The corresponding Port Data direction register bit is a logic 0 (configured as an input).
3. The I bit is cleared.

For example, to use a Port B pin as an interrupt on the 68HC705C8A, one must program a one to the Port B pullup bit (PBPUx) in MOR1, and program a 0 in the Port B data direction bit (DDRBx).

The method of enabling external interrupts on ports varies among MCUs. Consult the data book for the MCU you are using. In most cases, the additional interrupt lines are internally ORed with the IRQ line to form one interrupt source. The port interrupt lines are subjected to the same timing and sensitivity (edge/edge and level) considerations as the normal IRQ line.

IMPORTANT:
BIH or BIL instructions test voltages on the physical IRQ pin. The BIH or BIL instruction may not be used to test for port interrupt pin status. These interrupt pins should be tested by reading the data register location for the pin.

On all the ROM devices (68HC05B6,HC05B8, 68HC05B16, 68HC05B32) there are two mask options that affect the state of the watchdog . These are:

1. WATCHDOG STATE AFTER POR AND RESET : ENABLED or DISABLED

2. WATCHDOG STATE AFTER WAIT INSTRUCTION: ENABLED or DISABLED

WAIT MODE
With mask option 2 ENABLED and the MCU enters WAIT mode with the watchdog on, the watchdog circuit may not be refreshed before the time-out period lapses. This is because no CPU instructions are executed in WAIT mode and so no refresh of the watchdog counter can occur. Thus after the watchdog times out a reset will be generated, bring the MCU out of wait mode. If mask option 2. is DISABLED then the watchdog counter is reset and disabled. On exiting WAIT mode (via any interrupt) the watchdog will be enabled again and resume normal operation. If WAIT mode is exited via an external reset then the watchdog will resume the state as dictated by mask option 1.

On the EPROM devices (68HC705B5, 68HC705B16, and 68HC705B32) the two mask options are replaced by two bits located in the MASK OPTION* register, RWAT and WWAT. These bits are EPROM cells that when in the erased state the option is

disabled. Programming these bits to a '1' will enable the relevant mask option.

MCU	Addr of MOR
HC705B5	$1EFE
HC705B16	$3DFE
HC705B32	$7FDE

In the case of the watchdog being disabled after POR and reset the user can enable it by writing a '1' to WDOG bit. This will clear the watchdog counter and enable counting. To ensure there is no watchdog time-out , thus causing a reset, the WDOG bit must be regularly updated by writing a '1' to the watchdog refresh bit. Writing a '0' to the WDOG bit will have no effect on the watchdog system.

RESET
If the watchdog is allowed to time-out, a reset is generated. The reset is achieved by activating a pull down transistor connected internally to the RESET pin. This causes the MCU and all other functional blocks to be reset, as would be exhibited with an external reset. The external pull up resistance to V_DD should be greater than 30 Kohms to ensure that the watchdog reset is executed correctly. If this load is decreased, then the watchdog reset may not occur. The watchdog reset will normally be seen as an active low pulse of three oscillator cycles. Once the watchdog reset occurs, the MCU will monitor the RESET pin until a logic 0 is seen, then switch off the pull down transistor. This means that if a large capacitor is used for a long power-on reset time, the watchdog reset will not actually occur until the capacitor has been discharged to a logic 0. The pull down device has an equivalent resistance to V_SS of approximately 200 ohms. The MCU will accept a V_OL of a maximum 1.8 V. Discharge Equation:

This means that the MCU will not recognize a reset until approximately 10mS after the watchdog reset. After the watchdog reset has occurred the watchdog system will be in the state dictated by mask option 1. If the watchdog is to be enabled after reset then the watchdog counter also will be reset.

STOP
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is executed while the watchdog is enabled, then a watchdog reset will occur as if there was a watchdog time-out. In the case of a watchdog reset due to a STOP instruction, the oscillator will not be affected, thus there will be no tPORL cycles start-up delay. After the watchdog reset has occurred the watchdog system will be in the state as dictated by mask option 1. If the watchdog is to be enabled after reset the watchdog counter will be also be reset.

Time-out Period
The watchdog counter is a 3-stage counter which is clocked from the carry output from bit7 of the free running timer. A time-out will occur when the 3-stage counter has the value '7'. Once the watchdog reset has occurred the counter will also be reset to 0. Writing a '1' to the WDOG bit will clear the 3-stage counter to 0.

The watchdog can be enabled at any time with software. Therefore, the time-out period of the first count can vary depending on the carry output of bit 7 of the free running timer. The minimum time out period would be 6 states, and the maximum time out period is 7 states of the watchdog counter.

Minimum time-out period = 6 states of the watchdog Timer = 6 x 1024 CPU cycles = 3072 CPU cycles Maximum time-out period = 7 states of the watchdog Timer = 7 x 1024 CPU cycles = 3584 CPU cycles

Software Control
When implementing the watchdog, care should be taken on the number of places the watchdog is refreshed by the user software. In the case of the 68HC05B6 the minimum time-out is 3072 CPU cycles, which for an average of 4 cycles per instruction would be 768 instructions. A good design would be that the software would refresh the watchdog approximately every 700 instructions. This would allow a minimum number of watchdog refresh instructions in the user software, thus reducing the probability of code run-away refreshing the watchdog.

In the case of the larger ROM devices as with the 68HC05B16 and 68HC05B32, be careful that the ROM memory map does not have a refresh of the watchdog in every 1 Kbyte of code. This would make the chance of a watchdog time-out less if runaway was to occur. A small main loop with one refresh of the watchdog is the ideal scenario, where the main loop is a series to JSR (jump to subroutine) instructions. Watchdog refreshes should be avoided in interrupt routines and subroutines if possible to avoid run-away code refreshing the watchdog.

The triggering mode of an external interrupt is selectable in both C9A and C12 mode as either edge-only triggered or edge and level triggered. This trigger option is determined by the setting of the IRQ bit in C9A Option Register when the device is in C9A emulation mode and by the setting of the C12IRQ bit in the C12 Mask Option Register when the device is in C12 emulation mode. The setting is applicable to the Port B interrupts, when enabled, and for the IRQ interrupt.

The SOSCD (Short Oscillator Delay Bit) controls the oscillator stabilization counter and is located in the MOR (mask option register). Coming out of stop mode, the normal stabilization time is 4064 tcyc. By enabling the SOSCD (writing a logic 1) the oscillator stabilization delay is shortened to 16 cycles. This may cause wakeup from STOP functions or POR (power-on reset) to be inconsistent with some oscillator circuits. In newer mask sets, the SOSCD is shortened to 128 cycles as opposed to 16 cycles. This should provide ample time for a good oscillator to stabilize.

old mask set: F44T

new mask set: G58F (RC) / G63P (crystal)

The reset line does not have an internal pull up resistor. It is recommended that a low-voltage inhibit circuit such as the MC33064 be used. The MC33064 will hold the reset line low any time VCC is below the proper operating voltage. An RC can also be placed on the reset line which will pull it high slower than VCC. Using just a pull up resistor is not recommended because the reset line needs a delay at power-on to get a good reset.

An interrupt is occurring for a CAN module, a carry-over from the 68HC705X16 mask. Normally the CAN module in the 68HC705B16 is disabled and a CAN interrupt should not be possible. However, the CAN module circuitry in the 68HC705B16, mask set D28J only (it has been corrected in mask set F56K), may create a pending interrupt immediately after a POWER-ON RESET. That is, when the 68HC705B16 is first powered on, there may be a pending CAN interrupt and the device will service try to service it when interrupts are enabled (by means of a CLI instruction). If the CAN interrupt vector is not initialized to service valid code and a CAN interrupt occurs, the device will very likely run away.

The CAN interrupt's vector location is $3FF0-$3FF1. This is the only interrupt in the device that uses this vector address, and the 68HC705B16 with this mask set may require that a second reset occur after the POR. As the data book suggests, the best way to implement this is to start the watchdog timer after the POR. This is done automatically if the device has the mask option that enables the watchdog upon reset. If this is not the case, the watchdog can be started in software by setting the WDOG bit in the Miscellaneous Register. The watchdog can then be stopped by issuing the STOP instruction, at which time the watchdog reset will occur as if a watchdog time out occurred, which causes the CPU to fetch the address at the RESET vector location ($3FFE-$3FFF). After this second reset has occurred, the device is in a normal operating mode. This process can be done in an interrupt service routine whose vector is stored at $3FF0-$3FF1. The routine itself should have the following:

CANIRQ	BSET0,$0C	;Start watchdog (may not be needed if
		;mask option enables the watchdog)
	STOP	;Causes system reset as if a watchdog timeout has occurred
		;vectors to address specified by $3FFE-$3FFF

When the watchdog resets the circuit, the CAN is then correctly reset and normal execution of the main program can start without being interrupted by the CAN and without re-enabling the watchdog.

It should be noted that in some cases the problem is intermittent and may not appear at each power on. It is also independent of the external RESET circuitry. The problem does not exist on the 68HC05B16 (non-EPROM) device. The time lost between the end of the power-on reset sequence and the watchdog reset is equivalent to 8192 machine cycles (4 ms with 4 MHz crystal).

One alternative to interrupt-driven routines is polling routines. In a polling situation, status register flags are monitored periodically to determine if service is needed. An example would be monitoring the Serial Port Interface Flag (SPIF) in the SIOP Status Register (SSR) to determine if a data transfer has been completed.

This technique can be easier to implement than vectored interrupts. It can be used when responsiveness is not as critical or when tasks should be serviced at predictable intervals.

The endurance of the EEPROM in the B16 is specified to be at least 10,000 write/erase cycles, while the data retention is specified to be 10 years @ 85 degrees C. Programming time should be kept to a minimum, as the aggregate amount of time that the programming voltage is applied to a cell directly affects the cells longevity. The specification for both programming and erasing time is 10 milliseconds, but a cell can be programmed sufficiently most of the time in 400 microseconds to 1.2 milliseconds. Using a bump programming algorithm that programs in short increments, like a millisecond, and checks for successful write/erase after each bump before programming again, will result in better endurance for the EEPROM.

Symptom
At irregular times the 68HC05 performs the reset sequence. Instead of fetching an interrupt vector in the range from $FFF0 - $FFFD, the processor fetches the reset vector at $FFFE.

Explanation
This behavior occurs when a peripheral module raises an interrupt, while the currently executed instruction disables or resets this interrupt. The interrupt is recognized by the CPU05 during the opcode fetch cycle.

Since the 68HC05 does not interrupt an instruction, the actual interrupt processing is delayed till the end of this instruction. If, however, this instruction removes the source of the interrupt, the CPU does not know which originating interrupt line the reset vector fetched.

Example 1:
BSET RR,CTL ; set the reset bit in the CAN module

By setting the reset bit, all interrupts pending are cleared. So if a receive interrupt occurs just when the BSET opcode is fetched, this scenario occurs.

Example 2:
BCLR ICIE,TCR1 ; disable input capture by clearing the enable bit

By resetting the interrupt enable bit a interrupt output line is driven to zero. So if a valid input edge occurs at the beginning of this sequence we have the scenario.

Fix:
The fix is to disable the interrupt while modifying the enable bits.
E.g.
SEI
BSET RR,CTL
CLI

This should be done for any sequence affecting interrupt handling. In general disabling interrupts related to external asynchronous events should be performed with caution.

Remark:
In many textbooks this behavior is described as "spurious interrupt", and different MCUs handle it differently.

Examples of similar scenario with other MCUs

• The 68K has a special vector for it.
• The 68HC12 shares it with the SWI vector

Sympton:
This problem is usually a marginal rise time or stability issue with the application power supply. It is typical that the problem will be reported as a device power-on repetitive reset problem.

Explanation:
First ensure that watchdog or illegal address reset possibilities have been considered.

To eliminate any device related reset problem, remove or isolate the application power supply from the device and temporarily connect a bench DC power supply with a rise time of a few milliseconds. This should provide a clean power source and eliminate, or at least minimize, possible power supply rise time, spike, or oscillatory issues.

If this procedure proves successful, the customer should be advised to improve the performance of the application power supply. This may involve component adjustment for shorter rise time, ripple reduction, or improved noise immunity.

Here is the general procedure of interrupts:

1. An interrupt is triggered.
2. Current instruction is completed first.
3. Global interrupt mask is inspected to see if interrupts are masked or not i.e. in CCR, I = 1 or 0 .
4. If interrupts aren't masked i.e. I = 0 then CCR, accumulator, index register and program counter are pushed onto the stack.
5. Global interrupts are then masked i.e. I is set to 1 in the CCR.
6. Corresponding vector is loaded into the PC.
7. Interrupt service routine is carried out (within ISR, local interrupt mask should be cleared as soon as possible to capture further interrupts).
8. Registers from the stack are recovered via an RTI instruction, NOT an RTS one. Note here that the I bit will recover it's original status from the reloading of the CCR i.e. I = 0

   Pending interrupts retain their priority levels when the I bit is set, the highest priority routine (if it is pending) will be serviced as soon as the I bit is cleared again (in step 8).

Here is the general procedure of interrupts:

1. An interrupt is triggered.
2. Current instruction is completed first.
3. Global interrupt mask is inspected to see if interrupts are masked or not i.e. in CCR, I = 1 or 0 .
4. If interrupts aren't masked i.e. I = 0 then CCR, accumulator, index register and program counter are pushed onto the stack.
5. Global interrupts are then masked i.e. I is set to 1 in the CCR.
6. Corresponding vector is loaded into the PC.
7. Interrupt service routine is carried out (within ISR, local interrupt mask should be cleared as soon as possible to capture further interrupts).
8. Registers from the stack are recovered via an RTI instruction, NOT an RTS one. Note here that the I bit will recover it's original status from the reloading of the CCR i.e. I = 0

   Pending interrupts retain their priority levels when the I bit is set, the highest priority routine (if it is pending) will be serviced as soon as the I bit is cleared again (in step 8).

View the example code that demonstrates the implementation of interrupts, including setup, ISRs, interrupt arbitration, and initialization of interrupt vectors.

The sensitivity of the IRQ pin, in most parts, is selectable through an Option Register or Mask Option Register. This pin can be configured for negative-edge or negative-edge and level-sensitive triggering. If configured for level-sensitive triggering, an external pull up resistor should be connected to the IRQ pin.

The specific requirements of the IRQ pin signal are documented in each part's technical data book, in the control timing specification.

Under certain conditions, an anomaly occurs when disabling interrupts. This problem was first discovered with the Real Time Interrupt on the 68HC705BD8 (BlueKat). The scenario is:

Starting conditions: Real Time Interrupt is enabled (RTIE = 1) I bit in CCR is cleared.

To disable the interrupt, to do a time critical task, then the code normally would be seen as

Notice that the I bit is left at '0'. Using this code it was discovered that the MCU would sometimes jump to the RESET routine, even though no external reset, watchdog, or s/w "JUMP TO" were seen.

Further investigations showed that if the MCU were to receive an interrupt while executing the disable of that interrupt, then this would happen:

1. Interrupt latched and RTIF bit set
2. Execution of current instruction completed (thus disabling the interrupt)
3. PC, Acc, Xreg, CCR pushed onto stack
4. CPU checks what interrupt had occurred and fetches the relevant vector

At the last point, the RTIE bit overrides the RTIF bit (or signal) that goes to the "Interrupt Priority" logic. Because of this, the CPU sees that no interrupt is pending, so defaults and fetches the RESET Vector.

In software, this can be overcome by inserting an SEI instruction before disabling the interrupt.

This scenario can be replicated on all 68HC05 devices with the Real Time Interrupt on-board. Further investigation of other interrupts on 68HC05s are being made, and initial findings are that there will be a possibility of this scenario happening with other interrupts.

NOTE: Most customers may never see this scenario, as normally an interrupt is enabled and never disabled thereafter.

An external interrupt event is latched after a small synchronization delay. This latch causes the interrupt process to occur, and after nine cycles the IRQ vector location is read and the latch is cleared.

Another external interrupt pulse could be latched during the IRQ service routine. In this case, with the 68HC05 Family, there is no way to avoid the servicing of the pending interrupt upon returning from the current interrupt (issuing the RTI instruction). When returning from the current interrupt, the I bit will be returned to its value prior to the interrupt.

In the 68HC08 Family, the ISCR (Interrupt Status and Control Register) contains ACK (Acknowledge) bits which can be written to to clear the status of the interrupt latch. In this way, a pending interrupt can be cancelled.

Yes. The time it takes to process an interrupt is extremely important. An interrupt should be serviced and returned from as quickly as possible. The duration of the interrupt routine will determine how quickly interrupts may happen.

Consider the output compare function of the timer. If the output compare interrupt is used to generate a square wave on the TCMP pin, an interrupt must be generated twice for every period of the desired waveform. If a 10 kHz signal is to be generated, a timer interrupt needs to occur every 50 s. At an internal operating frequency of 2 MHz, a processor clock cycle takes 0.5 s. This would require the interrupt routine to take no longer than 100 clock cycles to execute.

It is important to include the time to vector to the interrupt routine when calculating the speed of the software. It takes nine clock cycles to stack the current program context (the same amount of time as an RTI) before the program counter jumps to the vector address. This should be included in the total clock cycle count of the interrupt routine.

Bottom line: an interrupt cannot be processed faster than the worst-case duration of its software routine.

The stack pointer can be affected in three ways:

1. The RSP instruction resets the stack pointer to location $00FF.
2. A subroutine call (BSR or JSR instruction) will occupy two locations on the stack.
3. An interrupt uses five locations on the stack.

Software will determine how the stack is affected by interrupts. If the user chooses to enable interrupts inside an interrupt routine, then nested interrupts may occur. In this instance, the stack will grow with each interrupt. The stack pointer can address 64 locations. If 64 locations are exceeded, the stack pointer wraps and loses the previously stored information. Care should be taken to avoid this condition.

NOTE: To maintain 68HC05 compatibility, interrupts on the 68HC08 Family do not stack the high byte (H) of the index register. If 68HC08 interrupt code modifies H, it is the user's responsibility to save and restore it.

Several behaviors are symptomatic of EEPROM failure or failing. They are:

• A cell takes progressively longer to be programmed or erased.
• Data retention time becomes shorter.
• A single bit or an entire byte is stuck at a certain value and cannot be erased.
• There are disturb problems when programming such that when one bit is programmed as a 1, neighboring bits are erroneously programmed as 1 also. This usually happens when program times have to be lengthened way beyond what the normal programming time is.
• A catastrophic failure occurs where nothing in EEPROM can be programmed or erased. This situation may occur if a short has developed in the array such that it disables adequate charge from being supplied to a cell being programmed.

It is good programming practice to address all interrupt vectors, including those that are not used. There are two ways to approach this. One method is to point all unused vectors to an RTI instruction. If a spurious interrupt occurs for some reason, the processor will simply return control and will not get lost.

An example of code to address unused interrupts:

The hazard of using the previous method of addressing unused interrupts is that it may conceal problems which the user wants to be made aware of. To avoid this, consider pointing the unused vectors to a routine which toggles an I/O pin or gives some other indication of a possible problem.

A more fault-tolerant method of handling unused interrupts is to use a "trap" with a COP (Computer Operating Properly) watchdog. This method, with a COP enabled, traps unwanted interrupts in a loop, waiting for a COP reset. This provides a way of resetting the microcontroller when an unexpected condition occurs.

An example of this technique:

NOTE: In certain parts which rely on the values of the user vectors for security, assigning identical address values to unused interrupts may not be acceptable. If this is a consideration, the trap/unused code could be duplicated in different memory locations to further enhance security.

The function of the RESET pin can differ from part to part. In some parts this pin is an input only. In other parts, the RESET pin can indicate an internal exception, driven by a COP or clock monitor reset.

For example, the 68HC705C8A has both a programmable and a non-programmable COP. The programmable COP will pull the RESET pin low on an internal reset. However, the non-programmable COP will not pull the RESET pin low when it internally resets the MCU. This behavior provides compatibility with older C4A and C8 MCU designs.

When using interrupts which share the same vector, the interrupt service routine at the address pointed to by the interrupt vector must perform arbitration to determine which source caused the interrupt. This can be done by monitoring the flag bits in the appropriate status register. The flag bits will indicate which source caused the interrupt. Of course, arbitration is unnecessary if only one interrupt source for a shared vector is enabled.

Using the 68HC705P6A MCU as an example, the Timer Vector ($1FF8 to $1FF9) is shared by three interrupt sources: Input Capture, Output Compare, and Timer Overflow. Because an interrupt from these sources will cause a program to jump to the same address, the interrupt service routine must resolve the origin of the interrupt. The Timer Status Register (TSR) contains flag bits for the three timer interrupt sources.

Once the interrupt source is determined and has been serviced, it is very important to clear the interrupt flag in the status register. If this is not done, a duplicate interrupt may occur after returning from the current one. Consult the particular MCU's data book for details on clearing its flag bits.

Maskable interrupts are globally enabled by clearing the I bit in the Condition Code Register (CCR). Use the CLI instruction to clear the I bit. Use the SEI instruction to set the I bit, thus inhibiting interrupts from being serviced.

The individual interrupts generated by the MCU modules (SCI, SPI, Timer, etc.) are enabled or disabled by their enable bits in the applicable control registers. To enable these types of interrupts, both the I bit and the enable bits must be appropriately configured. This allows a programmer to implement an application-specific combination of interrupts.

Take the 68HC705P6A MCU as an example. If one wanted to use the input capture function of the timer subsystem to cause an interrupt, the programmer would need to set the Input Capture Interrupt Enable (ICIE) bit of the Timer Control Register (TCR), then use the CLI instruction to start servicing interrupts. The Timer Vector ($1FF8 to $1FF9) should contain the address of the timer's interrupt service routine.

A software interrupt is non-maskable. Therefore, it is always enabled. The I bit has no effect on execution of the SWI instruction.

IMPORTANT:
On reset, the I bit is set. Therefore, it is necessary to clear the I bit before interrupts are expected to be serviced. To properly set up interrupts, the programmer should always configure control registers, set/clear interrupt enable bits, then clear the I bit.

The security bit in the 68HC705B16, implemented as bit 0 of the Options register ($100) in EEPROM and referred to as SEC, prevents entry into non-user mode when cleared and thus disallows external access to EPROM and EEPROM1. EEPROM1 is a 256-byte array from $100 to $1FF, while EPROM is the entire programming array from $300 to $3DFF and the user vector area from $3FF2 to $3FFF. When the SEC bit is set, it is in the erased state and access to these memory blocks are enabled in non-user mode. Once activated, this bit can only be deactivated in this OTP device by erasing this EEPROM bit in user mode.

The Options register, since it is within the first 32 bytes of the EEPROM array from $100 to $11F, is not protected from user-mode write/erase. This protection, which only protects the rest of EEPROM from $120 to $1FF, is enabled by the activation of the EEPROM protection bit, which is located at bit 1 of the Options register and is referred to as EE1P. This write protection, however, is only enforced in user mode, not in bootstrap mode.

Since the security bit, as well as the EEP1 bit, is implemented in EEPROM, it is modified by the use of the on-board charge pump and the proper manipulation of bits in the EEPROM control register. Note that the erased state of EEPROM is 1, so that each of these two functions is deactivated when their respective bit is high.

Interrupts fall into three categories: reset, software, and hardware.

A reset condition is similar to an interrupt, because it causes the MCU to fetch a new address for the program counter and sets the I bit to mask interrupts. The processor is configured to a known state as described in the data book for the MCU being used. Resets can be caused by a signal on the external RESET pin or an internal reset signal which can be caused by the COP module or the clock monitor.

A software interrupt occurs as a result of the SWI instruction. A software interrupt causes the same actions as a hardware interrupt; the program context is stacked, the I bit is set, and the interrupt vector is fetched. Another important difference between software and hardware interrupts is that context is stacked, the I bit is set, and the interrupt vector is fetched. The important difference between software and hardware interrupts is that the software interrupt is nonmaskable. In other words, the value of the I bit has no effect on the software interrupt. A software interrupt is always executed.

A hardware interrupt is generated by internal or external hardware conditions. This type of interrupt can be initiated by hardware pins or modules. Hardware interrupts are maskable, so they can be recognized only with the I bit cleared. Each module has its own interrupt vector, but interrupt sources within the same module can share the same vector. For this reason, it is important to arbitrate interrupts which share an interrupt vector.

Common MCU hardware interrupt sources:

IRQ:
The IRQ pin can be used to trigger external hardware interrupts. Depending on the MCU configuration, a logic low or a high-to-low transition on this pin will cause an IRQ interrupt. This interrupt can be used to monitor external systems or events.

Timer:
The 16-bit timer on a Motorola MCU can generate several different interrupts, depending on the particular part used. The output compare, input capture, and timer overflow functions of the timer module can generate interrupts. Some parts also have a real-time interrupt feature. These types of interrupts can be used to process events based on time references.

SCI/SPI:
Parts equipped with SCI or SPI serial ports can generate a variety of interrupts, depending on the part used. These include receive register full, transmit register empty, and transmission complete interrupts. These types of interrupts can be used to process serial communications events.

I/O Port Pins:
Some Motorola MCUs have the ability to use I/O port pins to generate hardware interrupts. These combine with the IRQ pin to form one source of hardware interrupts. Each interrupt source has a specific priority, determined by the device. For information on interrupt priorities, consult the data book for the device.

If an enabled interrupt occurs, the instruction in progress is completed. The processor then saves the current values of the program counter, accumulator, index register, and condition code register onto the stack. The interrupt mask (I bit) is set to prevent additional interrupts.

Each interrupt source (IRQ, Timer, SCI, SPI, SWI) has its own interrupt vector, typically located in the last block of the memory map. These locations can vary between parts. The high and low bytes of a particular interrupt vector tell the processor where to find the interrupt's service routine. When an interrupt occurs, this address is fetched and loaded into the program counter.

To return from the interrupt, the RTI instruction is used. This should be the last instruction in an interrupt's service routine. The RTI instruction restores the values of the condition code register, accumulator, index register, and program counter from the stack. This returns the processor to its state before the interrupt occurred. The I bit is reset if the I bit stored on the stack is 0.

512 bytes of RAM reside in the memory map from $40 to $23F. The stack is located in its standard location starting at $FF and extending down to $C0 (contrary to a statement in the 68HC705L16's data book). The first 192 bytes of RAM, from $40 to $FF, can be accessed by direct addressing, while the remaining 320 bytes above $FF are accessed by extended addressing.

An interrupt provides a method of temporarily stopping normal program execution to perform a given task. After the task has been completed, normal processing can be resumed.

Interrupts provide a fast, efficient, and automated technique to process tasks and peripherals. They are especially useful for time-critical responses to I/O events or for tasks which require attention at irregular intervals.

The unprogrammed state for the 68HC705C8A EPROM is 0.

The stack space for the 68HC705P6A, as with most 68HC05's, is from $FF to $C0. If the stack overflows, that is, if the amount of data written to the stack fills this 64-byte RAM area and causes the pointer to go past $C0, the pointer wraps around to $FF where data (return address, etc.) are overwritten. This will, of course, prevent return from routines or interrupts whose return addresses were stored there. For this reason, it is a good idea to keep interrupts disabled in interrupt service routines. Note that for 68HC08's, the stack pointer has no such restriction and can be located, either by automatic decrement or by programmatic positioning using the TXS instruction, anywhere in the 16-bit memory area.

No. The mask option register, which is implemented in EPROM, cannot be programmed in user mode, only in expanded test mode. All other EPROM locations can be programmed in user mode by applying the necessary programming voltage on the IRQ/ V_PP pin and manipulating the bits in the EPROM Programming Register ($0018) appropriately.

One of two ranges can be selected for block protection. The entire FLASH array can be protected by setting any, or any combination, of bits 0 - 2 of the block protection register. Setting bit 3 of this register, with bits 0 - 2 cleared, will select the range $C000-$FFFF for protection. In this latter protection setting, the range $B000-$BFFF is left unprotected and may be erased and reprogrammed without turning off block protection. Block protection can be disabled only when there is high voltage (V_DD + 2.5 V) on IRQ, and is done by erasing the range (row, 8-row block, array or full array) in which the block protection register ($FF80) resides.

The page program procedure as specified in the FLASH section of the 68HC908GP20 data book requires that a write is made to each address being programmed with the data intended to reside there. If a byte in the page to be programmed is not in the FLASH array, then omit the write to this location. You may also want to modify the normal page verification stage to not include checks for bytes out of the FLASH array to avoid erroneous verification failures.

No. FLASH can be programmed with no external high voltage and with the device powered as low as 3.0 volts. Note, however, that block protection can be disabled only when there is high voltage (V_DD + 2.5 V) on IRQ and that this voltage is required to enter monitor mode when the device is not blank. This mode of operation is necessary when the device is blank, or it may be preferred for programming, depending on the method and tools selected for FLASH programming.

Yes. To enable the low-voltage mode of the FLASH charge pump, which is required whenever V_DD is less than 3.6 volts, the FLASH Charge Pump Select Gate V_OLtage Low- V_OLtage Enable Bit (PMPSGVLVEN) in the CONFIG1 register needs to be set. To conserve power, this bit should be cleared when not programming at a V_DD voltage lower than 3.6 volts.

EPROM and OTP devices are often supersets of mask ROM devices. Be sure to check both the mask ROM data book and the OTP data book when doing your design. Pay careful attention to mask option differences. For example, the following are two potential problem areas of the 68HC705C8A and 68HC05C8A if the user is not aware of these differences:

• The expanded RAM map (from $30-$4F and $100-$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A.

• The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.

Margin read is a process which places a more stringent condition on the bit cell than what takes place during a normal read operation. This condition results in a more negative gate voltage being applied to the bit cell for a period of time that is eight cycles longer than during a normal read. Long-term data retention is assured when correct data is read under these conditions. This type of read is performed after each progressive program bump in the smart programming algorithm to see if the bytes in the page have been programmed adequately or whether the page needs to go through another program/read cycle.

The C8A/C9A has three areas of RAM: the 176-byte main block at $50-$FF and two smaller blocks which share memory map space with program memory (either EPROM in the 68HC705 or ROM in the 68HC05). These two smaller blocks, called RAM0 RAM and RAM1 RAM, are enabled by the RAM0 and RAM1 bits of the Option register. The default (reset) state of these bits is low, which disables these RAM blocks in favor of enabling program memory that is mapped in these ranges.

The RAM0 and RAM1 bits of the Option register can be changed at any time during normal operation. When one of these RAM blocks is enabled and something written to one or more of its cells and then the block is disabled and later re-enabled, the RAM's content will be retained as long as power has not been interrupted.

When the A/D converter is enabled, pins PC3-PC6 become analog inputs. Any unused analog inputs may be used as digital inputs. However, they may not be used as digital output pins. Only pins PC0-PC2 can be used as digital output pins when the A/D converter is enabled

EPROM and OTP devices are often supersets of mask ROM devices. Be sure to check both the mask ROM databook and the OTP data book when doing your design. Pay careful attention to mask option differences and the following:

• The expanded RAM map (from $30-$4F and $100-$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A.

• The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.

The voltage between VREFL and VREFH should be at least 2.5 V for A/D accuracy. Lower values will cause more inaccuracy for A/D conversions. The converter will still operate.

• Reduce the noise that is introduced into the A/D subsystem by using careful lay out to separate the noisy signals from the sensitive A/D signals. Where complete separation is not cost effective, reduce the noise coupling as much as possible. Refer to application note AN1059/D, System Design and Layout Techniques for Noise Reduction in MCU Based Systems.
• If the bus clock is less than 1 MHz, turn on the A/D's separate RC oscillator. Allow time for the RC oscillator to stabilize before beginning conversions. The RC stabilization time, Tadrc, is specified in the device data books.
• After turning on the A/D subsystem, allow time for the A/D on current to stabilize before beginning conversions. The ADC on current stabilization time, Tadon, is specified in the device data books.
• Make sure the source impedance is not too large. Errors caused by the input leakage current of the A/D increases proportionately to the source impedance. If possible, have the reference voltage greater than 4 volts. Otherwise, accuracy may decrease proportionately as V_RH is reduced less than 4 volts.
• If bandwidth permits, take multiple conversions and average the results to reduce the impact of injected noise.

If the input pin voltage is driven below V_SS, it may cause a disruption in the A/D conversion process. Anything greater than a half diode drop (0.3 V) below V_SS will cause permanent damage to the A/D input pins. This will also affect any adjacent analog pins. This is due to the diode connected to V_SS. To help prevent damage, a series resistor may be added. A recommended value is R = 1 k ohms. Any value greater than 10 k ohms will cause input leakage leading to A/D accuracy being degraded.

VREFH must be less than or equal to V_DDA, while VREFL must be greater than or equal to B_SSA.

The SCI has the option of allowing full-duplex communication. The SCI transmitter and receiver operate independently of one another, even though they are controlled through the same register. The SCI data register (SCDR) is controlled by the internal read/write signal. This means that when data is written to the register, it is a transmitter, and when data is read, it is a receiver. SCCR2 is the control register for the SCI. Selecting the RE or TE bit (bits 2 and 3 respectively) enables the receiver and/or transceiver.

Adding a series resistor to a pin can cause input leakage which would cause the A/D accuracy to degrade. Some users may want to include a series resistor to give some protection for operating below A/D voltage specifications. See the minimum voltage FAQ that follows for more information.

The method of clearing the Mode Fault Flag (MODF) is different from the way the other two status bits of the SPSR, the Serial Transfer Complete Flag (SPIF), the Write Collision Flag (WCOL), are cleared. The following table explains the differences.

Flag	Clear Method
Serial Transfer Complete Flag (SPIF)	Read the SPSR with SPIF set, then read from or write to the SPDR.
Write Collision Flag (WCOL)	Read the SPSR with WCOL set, then read from or write to the SPDR.
Mode Fault Flag (MODF)	Read the SPSR with MODF set, then write to the SPCR.

No. To enable the SIOP, you must set the SPE bit in the SCR (SIOP Control Register, $000A). Port B data registers can still be written to. However, if you write to either port B register while a data transfer is occurring, you could corrupt the data that is being transferred. Also note that there are only three bits that may be used as I/Os (PB5:PB7).

The SIOP is similar to the SPI in that they are both synchronous communication systems. They are, however, different is some important ways:

1. The SIOP and the SPI clock rate selections are different. The SIOP, depending on the particular device, supports either a single data rate that is equal to the internal clock divided by 4 (i.e., the 68HC705P9) or a prescale of the internal clock. The prescaler in the 68HC705P6A and the 68HC705JJ7 offers a divide by 8, 16, 32, or 64, while the 68HC705P6 offers divide by 4, 8, 16, or 32. In slave mode, a device can accept an input clock as high as its internal clock divided by 4, and there is no lower limit on the input clock frequency. The SPI in nearly all devices allows a serial clock selection of internal clock divided by 2, 4, 16, or 32.
2. .In the SIOP, the polarity of the serial clock between transmissions is fixed at a high level, while the SPI allows for selection of this parameter.
3. In the SIOP, the phase of the serial clock is fixed at latching data on the falling edge of the clock, while the SPI allows for selection between rising and falling edges.
4. There is no slave select pin in the SIOP. The master is set and cannot be converted to a slave by an external signal. Additionally, the master cannot enable slave communication by clearing this I/O bit. Because there is no slave select pin in the SIOP, there is no need for a mode fault status bit like the one found in the SPI.
5. SIOP does not support an interrupt upon transmitting or receiving a byte of data as the SPI does.

Some confusion exists as to what, if anything, must be written into the DDRD when using the SCI subsystem. With the SPI subsystem, the DDRD must be written to define certain pins as outputs and certain pins as inputs (see the SPI section). However, with the SCI this is not the case. When the SCI is enabled, the affected pins automatically configure themselves to the proper input or output state. The DDRD need not be written to.

As its name implies, the Simple Serial Peripheral Interface, or SSPI, is a simplified version of the Serial Peripheral Interface, or SPI. There are a few minor differences between the two systems. The user should be aware of:

1. The SSPI allows selection of the order of bit transmission (DORD), while the SPI is automatically set to send the most significant bit out first.
2. The SPI allows selection of clock line polarity (CPOL) between transmissions while the SSPI is always high.
3. The SPI allows selection of clock phase for data transmission (CPHA), while the SSPI only clocks data on the rising edge of the clock.
4. The SPI allows for four clock rates (divide by 2, 4, 16 or 32 defined by SPR1 and SPR0 bits in the SPCR), while the SSPI allows for only two clock rates (divide by 2 or 16 defined by SPR0 in the SPCR).
5. The SPI supports a mode fault trap that would be sensed if the slave select (/SS) pin goes low while the MSTR bit is set. When this occurs, the MCU puts the SPI in slave mode, disables the SPI and sets the MODF bit in the SCSR. This feature allows for resolution of contention when more than one device in a linked system acts as a master in turn.

The following table shows the functional differences between the two systems.

For the pins that are used as SPI inputs (MISO for a master and MOSI, /SS and SCK for a slave), the setting of the DDR is not important. The pins will be configured as inputs regardless of the DDR setting. For pins that are used as SPI outputs (MOSI and SCK for a master and MISO for a slave), the setting of the DDR is important and must be set to reflect these pins as outputs.

The SCI+ (Serial Communication Interface +) system combines capabilities of both the synchronous SPI (Serial Peripheral Interface) and the asynchronous SCI. The SCI+ loses some of the functionality of the SPI but improves upon it with other features, while several of the features of the SCI are enhanced in the SCI+. Features of all three systems are contrasted in the table here.

Feature	SPI	SCI	SCI+
Transmission Type	Synchronous	Asynchronous	Synchronous/Asynchronous
Baud Rate	4 selectable rates; transmit rate = receive rate	32 selectable rates; transmit rate = receive rate	32 selectable rates; transmit and receive have same first prescaler stage (selectable 1 of 4), but have separate second prescaler stages (selectable 1 of 8); transmit rate does not have to equal receive rate
Data Bits	8 bits only	Selectable 8 or 9 bits	Selectable 8 or 9 bits
Master Mode Selection	Allows appointment of a bus master to control communication to/from slave(s)	N/A*	N/A
Port Enabling/ Wake-up Method	Enables receiving of data and the clock by a slave through the Slave Select (/SS) pin, pin also selects/deselects the master	TE and RE enables transmitting and receiving of data, respectively; Receiver Wake-up Enabled (RWU) bit enables wake-up method selected by WAKE bit; WAKE bit selects either address mark or idle line wake-up	TE and RE enables transmitting and receiving of data, respectively; Receiver Wake-up Enabled (RWU) bit enables wake-up method selected by WAKE bit; WAKE bit selects either address mark or idle line wake-up
Transmission Flags	One flag for completion of either transmit and receive	Separate flags for Transmit Complete (TE), Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Idle Line Detected (IDLE)	Separate flags for Transmit Complete (TE), Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Idle Line Detected (IDLE)
Error Flags	Write Collision (WCOL) and Mode Fault (MODF)	Overrun (OR), Noise (NF) and Framing (FE)	Overrun (OR), Noise (NF) and Framing (FE)
Interrupts	Single interrupt (SPIE) may be asserted upon the transmitting or receiving of 8 bits of data	Transmit data register empty (TIE), transmission complete (TCIE), receive data register full or receiver overrun (RIE), idle line (ILIE)	Transmit data register empty (TIE), transmission complete (TCIE), receive data register full or receiver overrun (RIE), idle line (ILIE)
Break Code Support	N/A	Send Break Code (SBK) bit enables continuous sending of break code	Send Break Code (SBK) bit enables continuous sending of break code
Clock Polarity/ Phase Control	Clock Polarity (CPOL) bit selects polarity of line between transmissions; Clock Phase (CPHA) bit selects rising or falling edge of clock to latch synchronous data	N/A	Clock Polarity (CPOL) bit selects polarity of line between transmissions; Clock Phase (CPHA) bit selects rising or falling edge of clock to latch synchronous data
Last Bit Clock	N/A	N/A	Last Bit Clock (LBCL) bit enables/disables clock signal on last (8th or 9th) bit transmitted

*N/A = not available or not applicable

Note that the SCI+ nomenclature in the 68HC05 Family has different connotations from the meaning of SCI+ in the 68HC11 Family. In the 68HC11's, the SCI+ expands on the number of baud rates that can be selected by providing a 13-bit prescaler. Unlike the 68HC05's SCI+, it does not add support for synchronous serial communication.

Do not use the DB, FCB, DW, or FDB pseudo-ops to reserve RAM space since they can corrupt the portion of the bootloader that is copied into RAM.

When reserving space for variables in RAM, use the DS or RMB pseudo-ops. These pseudo-ops reserve bytes by changing the location counter in the assembler only. They do not actually write to the S-record when assembling.

When initializing ROM or EPROM, use the DB or FCB Pseudo-Ops for eight bits and DW or FDB pseudo-ops for 16 bits.

Although the HC(7)05C9A appears to have the same Serial Peripheral Interface as the C8A device , note should be taken of the slight variation in Port D operation to avoid problems with use. As can be seen from the C9A memory map, Port D Data Direction Register at $07 allows the user to configure the port lines as either input or output (fixed as inputs on other Cx devices). When using the SPI function, the contents of this register affect the operation of the SPI as it shares port D with the I/O lines. If using the device as an SPI, the direction of SPI data must be set in DDRD ($07) in the same fashion as Port lines. ie. Storing the value $18 in DDRD ($07) configures SS (bit 5) as input SCK (bit 4) as output MOSI (bit 3) as output MISO (bit 2) as input.

This configuration will give the correct operating conditions to use the HC(7)05C9A device as an SPI master in the same fashion as other 68HC05Cx devices.

The Transmit interrupt, if enabled by having set the Transmit Interrupt Enable (TIE) bit, is triggered when the Transmit Data Register Empty (TDRE) bit becomes set. This occurs upon transfer of the data byte to the shift register. The shift register must then be emptied by shifting out each bit of the byte being transmitted. The Transmission Complete interrupt, if enabled by having set the Transmission Complete Interrupt Enable (TCIE) bit, is triggered when the Transmission Complete (TC) bit becomes set. This occurs only after the byte has been completely transferred out and the shift register is empty. It is therefore more efficient to cause a Transmit interrupt when the data register is empty so it can be loaded with the next byte of data while the shift register is transferring the prior byte.

The TDRE and the TC bits have a default value of 1 while the remaining bits of the SCSR (RDRF, IDLE, OR, NF, and FE) have a low default value. To clear the TDRE or the TC bits, first read the SCSR while the bit is set and then write to the SCDR. As soon as the data that was sent to the SCDR is transmitted, both of these bits will return to a high state. To clear one of the remaining bits, either cause a reset or first read the SCSR while the bit is set and then read the SCDR.

The wake-up feature of the SCI is enabled by setting the Receiver Wake-up (RWU) bit of the SCCR2. This will put the receiver to sleep, disabling receiver interrupts, until it is awakened by one of two ways. One wake-up method, address mark, which is implemented by setting the Wake-up Mode Select (WAKE) bit of the SCCR1, will cause the receiver to wake up when a byte of data is received which has a most significant bit of 1. The most significant bit will be bit 8 when 9-bit data mode is selected (M = 1), and bit 7 when 8-bit data mode is selected (M = 0). When this occurs, the hardware clears the RWU enabling interrupts, and the receiver would read the byte to see if it represents its own address and, if so, would process the message that follows. If the byte did not represent its address, then it would ignore the message as it own address and, if so, would process the message that follows. If the byte did not represent its address, then it would ignore the message as it is meant for another device and set the RWU bit once again.

The other wake-up method, idle line, which is implemented by clearing the WAKE bit, will cause the receiver to wake up whenever the line is idle, during which time 11 or 12 1's will appear on the receive line. This configuration requires that there be at least one character time of idle between messages to wake up sleeping receiver, but that there be no idle time between characters within a single message. Note that for both wake-up methods, the IDLE flag of the SCSR is disabled when the RWU bit is set which disables the idle interrupt

Using address mark wake-up requires a bit to be used to designate an address byte, which dictates the length of all other bytes of data. It relieves any concern about waking up receivers when there may be frequent idle states. This method would be favorable when specific receiver-directed messages rather than broadcasts are used extensively, especially if the messages are long (where reading an entire message intended for another receiver is prohibitive and where the address bit does not cause a serious overhead in the transmitted data. This would be so if the address range goes no higher than 127 and bit 7 could be used as the address bit, rather than having to make the character length nine bits to accommodate the address bit and at the same time causing all data to conform to the longer character length.

Idle wake-up is useful when an address bit would cause too much overhead on message lengths and where waking up because of idle time is of no concern or actually desirable. This configuration may be used when broadcasting data to multiple stations, and/or when there is frequent, almost continuous communication among stations on the link. In this scenario, a master can control the state of the receivers (whether they are in a dormant mode) by not allowing any idle time on the line.

The SIOP is configurable as a mask option to transmit the least or the most significant bit first. Normal configuration is most significant bit first.

The primary purpose of an MCU COP is to momentarily RESET the MCU when the MCU device is out of control: for example, in the case of software runaway. The MCU then will come out of RESET and will once again operate in a controlled manner.

The MCU COP is implemented in silicon as either a timer or a counter. The clock source driving the COP can be derived from the MCU bus clock or in some cases an on-chip RC oscillator. When the COP timer, or counter, reaches a predetermined value it generates a signal which will RESET the device - this value determines the COP TIMEOUT PERIOD. The minimum value of this period can be found in the device data book and will be quoted in terms of bus clock cycles or in terms of time versus bus frequency.

To prevent the COP from reaching its final value and therefore from RESETING the MCU, it must be REFRESHED. This operation must occur within the minimum COP TIMEOUT PERIOD. The method of refreshing the COP depends heavily on the COP implementation.

In the case of 68HC05 devices which have the MFT, or CORE TIMER, the general method is to write '0' to bit 0 of an address specified in the device data book. This will normally require a LOAD and STORE instruction (BSET/BCLR instructions cannot be used when the refresh address is out side page 0 memory i.e. out side the range $0000 - $00FF).

In most other 68HC05s, the COP is refreshed by storing the values $55 then $AA into the COPRST register. Some 68HC05s also have a CLOCK MONITOR RESET feature which will RESET the device if the device clock source is lost; for example, if the clock oscillator crystal was to become disconnected from the device.

When refreshing the COP, the following points should be considered:

1. Ideally, there should only be one instruction, or one section of code, that refreshes the COP.

   In some cases, multiple refresh instructions throughout the code are unavoidable. For example, where there is a possibility that the refresh may not occur within the time-out period even when the code is executing correctly. They should, however, be kept to a minimum. The reason for having one instruction, or section of code, to refresh the COP is that if the software runs away, it may find itself caught in a loop of code, a section of which refreshes the COP. If this happens the COP is being refreshed and the code is not executing correctly. The device will not RESET in this case.

2. The one instruction, or one section of code, that refreshes the COP should ideally be in the main code loop. We can be confident that the COP is being correctly refreshed when the refresh is in the main loop code and that the device operation is correctly monitored.

3. The one instruction, or one section of code, that refreshes the COP should ideally NOT be in a subroutine. However unlikely it may be, there is the possibility that the subroutine could be called by runaway code, especially if the watchdog subroutine address is in the STACK RAM.

4. The one instruction, or one section of code, that refreshes the COP should NOT be in a timer or other INTERRUPT routine. Although it may appear convenient to refresh the COP in a TIMER INTERRUPT routine, it is not good practice and should be avoided if possible. Interrupts, as indicated by their name, interrupt executing code, independent of whether the code is correct or incorrect (as in the case of runaway). There may be instances when the interrupts are the only possibility for COP refresh, for example if the device has to go into WAIT mode to reduce power consumption. In this case the work-around may be for other routines to set bits in RAM when these routines are operating correctly. These bits can then be tested in the interrupt routine and some level of confidence be given to correct operation. If the bits are incorrect the necessary recovery action may be carried out.

5. The MINIMUM time-out period must always be considered - see the data book for this value.

No. When the SIOP is enabled by setting the Serial Port Enable (SPE) bit of SCR high, the data direction register automatically is configured to set SCK as an output in master mode or as an input in slave mode, SDI as an input, and SDO as an output. If the SIOP is later disabled by clearing SPE, then the port DDR will revert to whatever it was previously set to.

The timer overflow function lets the user know when the timer counter has rolled over. This function is useful for extending the range of the timer subsystem.

For example, in the 68HC705C8A MCU, the timer counter has a range of 16 bits. This allows a resolution of 2us at an internal frequency of 2 MHz.

Timer frequency = 2 MHz/4 = 500 kHz

Timer period = 1/500 kHz = 2us

Timer overflow period = 2 us * 65,535 = 131 ms

If the number of timer overflows are counted through software, the range is extended at a resolution of 131 ms.

The timer overflow event can trigger an interrupt, or can be polled using the timer overflow flag (TOF).

Using the input capture function, an input signal is used to trigger a read of the free-running counter. When an external event is detected on the TCAP pin, the value of the timer counter is saved in the input capture register. In this way, the relative time the event occurred is recorded.

One use of input capture is to measure the period or the pulse width of a signal. By capturing the time of two successive edges of the same polarity, the time elapsed between periods can be determined. By capturing two alternate polarity edges, the width of a pulse can be determined. In either case, one could find the difference of the input capture registers at the time of the two events and use this difference to find the time elapsed between events (counter difference divided by the timer frequency).

The input capture function can be interrupt driven or can be polled using the input capture flag (ICF).

"

Listed here are popular Motorola MCUs and their available timer functions.

68HC05 Timer Features

MCU	Range	InputCapture	OutputCompare	Real-Time Interrupt	COP
705B16	16-bit	2	2	no	yes
705C8A	16-bit	1	1	no	yes
705C9A	16-bit	1	1	no	yes
705JJ7	16-bit	1	1	yes	yes
705JP7	16-bit	1	1	yes	yes
705J1A	8-bit	no	no	yes	yes
705KJ1	8-bit	no	no	yes	yes
805K3	8-bit	no	no	yes	yes
705L16*	16-bit	1	1	yes	yes
705P6A	16-bit	1	1	no	yes

^* The 68HC705L16 includes an additional, independent 8-bit event timer counter

The most important issue when programming the timer subsystem is code latency. The amount of time it takes to execute timer routines will determine the speed at which the timer subsystem can be used.

Example: producing a square wave signal using the interrupt-driven output compare function of the 68HC705C8A, running at an internal frequency of 2 MHz. At this bus frequency, the timer subsystem has a frequency of 500 kHz and a period of 2 us. Assume the routine which services the output compare interrupt takes 50 cycles (including the overhead of entering the interrupt) or 25 us. Because the code to set up an output compare pulse takes 25 us, this is the minimum pulse length that can be produced. This would limit the square wave output to a maximum attainable frequency of 20 kHz at a standard bus frequency of 2 MHz.

High-speed parts like the 68HSC705C8A, which provides a 4 MHz bus speed, can achieve even higher PWM frequencies. Using the example here, the 68HSC705C8A could achieve a square wave frequency of 40 kHz.

Another important programming consideration is the use of flags in the status register. In an interrupt-driven scheme, the interrupt sources of the timer subsystem share the same interrupt vector. Because of this, the interrupt service routine must determine which timer function caused the interrupt. This can be done through testing of the flags in the status register.

Once a timer interrupt is serviced, it is important to clear its flag in the status register. If the flag is not cleared after servicing the interrupt, then immediately after the return-from-interrupt (RTI) instruction, the same event will cause a duplicate interrupt.

For The 68HC08 Family Timer:

Programmers who use the TIM08 for PWM generation should note the following about the Timer Modulo Register. The Timer counts 0000 and the number in the Modulo Register as the timer ticks. Therefore, the frequency output from the timer channel is:

input / [prescaler * (modulo +1)]

Note the 1 added to the modulo value due to counting both 0000 and the modulo value.

The extra cycle is only .0015% of a period for a modulo value of $FFFF so it is below most measurement error. However, it becomes significant at lower modulo values. It is 3.1% of a period for a modulo value of $0020.

The real-time interrupt is a feature of some Motorola MCUs. It allows an interrupt to be generated at a constant interval. For example, the 68HC705J1A offers four programmable real-time interrupt rates.

The real-time interrupt feature is useful for implementing tasks which occur on a regular, periodic basis. Examples include checking for external events, periodic waking from a low power mode, running periodic maintenance tasks, etc.

The advantage of a real-time interrupt is that it doesn't require as much software overhead as the output compare function. The disadvantage is that it is not as flexible, offering a limited number of periods.

The timer control register (TCR) allows the user to control the timer subsystem functions. One important function of the TCR is to enable and disable interrupts generated by the timer subsystem. There is typically a bit for each of the timer interrupt sources (input capture, output compare, timer overflow, and real-time interrupt) which enables or disables its respective interrupt.

The TCR usually contains a bit (IEDG) which defines the active edge polarity of the TCAP signal for an input capture function. There is also a bit (OLVL) to define the logic level for output to the TCMP pin on a valid output compare.

The timer status register (TSR) contains flag bits, indicating the occurrence of the timer events (output compare, input capture, timer overflow, and real-time interrupt). Each flag drives its respective interrupt, if enabled. If the interrupt is not enabled, the flag still gets set and can be polled if desired. These flags can also be used to determine the source of a timer interrupt.

These flags should be cleared as the timer events are serviced. It is important to properly clear the flags, so the interrupt logic does not acknowledge duplicate interrupts. This is typically done by:

1. Accessing the timer status register (TSR) while the flag is set
2. Accessing the low byte of the appropriate counter register

Some parts, such as the 68HC705J1A, have a combined timer control and status register, and flags are cleared by writing to a flag reset bit in the register. For details on a particular part, consult the appropriate data book.

Both the timer registers and the alternate timer registers contain the current high and low bytes of the 16-bit counter. In most parts, these are read-only registers.

Reading the high byte of either the timer registers or the alternate timer registers will return the high byte of the counter and latch the value of the low byte into a buffer. Reading the low byte will return the value in the buffer, completing the read sequence. The value latched in the buffer will remain fixed, even if the high byte is read more than once before the low byte is read.

The difference between the two is that a read of the timer register low byte after reading the timer status register clears the timer overflow flag (TOF) bit. Reading the alternate timer register does not affect the TOF bit.

NOTE: The alternate register should be used to read the timer counter in all cases except when intending to clear TOF. This will avoid the possibility of the TOF being cleared unintentionally.

In most 68HC05 MCUs, the free-running counter can't be reset. One exception is the 68HC(7)05B16. In this MCU, a write to the timer registers causes the counter to be reset to a known value. Consult the appropriate data book for details.

The 68HC08 Family of MCUs does allow the counter timer to be reset.

A reset (external, internal, or power-on) always sets the timer counter to a known value, typically $0000 or $FFFC.

The output compare function allows an action to occur at a specific time. When the value programmed into the output compare register matches the value of the timer counter, a predefined output is generated on the TCMP pin (for 68HC05 MCUs) or other output pin.

One use of the output compare function is to produce a pulse of a specific duration. By controlling the OLVL (Output Level) bit and the value of the output compare register, the signal at the TCMP pin (or other pin) can be pulse-width (or pulse-length) modulated.

Another use of the output compare function is to generate a specific delay. In this case, one doesn't particularly care to generate an external signal, but use the timer as a programmable alarm clock. By using the output compare interrupt, one can set the timer for a particular value and continue processing. When the value in the output compare register matches the free-running timer, an interrupt is generated and the timer code can take over.

Output compare delays can also be used to generate edges that trigger or synchronize external events. In this case, the edge polarity is the controlling signal instead of the pulse length.

The output compare function can be interrupt driven or can be polled using the output compare flag (OCF).

The J1A is a fully static part which can operate with an internal bus speed from DC to 2 MHz. When trying to save power, it is recommended that you operate at the lowest possible frequency and use STOP mode as much as possible. When using an external crystal, use an AT-cut parallel resonant crystal.

The short oscillator delay is selected by setting the SOSCD bit in the MOR (bit 7, location $07F1). This is an EPROM register, so once programmed, it is permanently set.

The normal oscillator delay following reset or exit from stop mode is 4064*tcyc. When the short oscillator delay is enabled, the delay becomes 128*tcyc.

NOTE: The short delay period depends on the mask set of the device. For mask set F44T, the delay is 16*tcyc. For mask sets G58F and G63P, the delay is 128*tcyc.

The PLL is designed for use with a 16 kHz to 100 kHz reference signal, optimally with a 32 kHz crystal. If you use the PLL, the absolute highest value crystal is limited to 100 kHz.

Using an external (canned, square wave) oscillator, the fastest speed that can be used with the PLL is limited to 1.5 MHz. In the case of up to 1.5 MHz, the divider value R in the PLL control registers is used to divide down the crystal frequency to a reference frequency that falls within the 16 kHz to 100 kHz range. If an external clock higher than 1.5 MHz were used, the R value could not be high enough to reduce the reference signal to less than 100 kHz.

The crystal option 68HC908GP20 is only designed to work with a 32 kHz to 100 kHz crystal. Faster crystals should not be used. If the crystal option is selected, the user must connect a 32 kHz to 100 kHz crystal and use the PLL to generate desired bus speeds up to 8 MHz.

Page 2-7 of the Product Preview (Rev 2.0) of the 68HC05L1/705L1 explains the Control Registers of the 68HC05L1. Control Register, CR1, at address $0A contains bit 4, the DON bit.

DON, bit 4 ---------- 0 = Turn off LCD 1 = Turn on LCD

The one exception when the OSC will still be running in STOP mode is when the LCD is not turned off before going into STOP mode. Make sure to turn off the LCD by clearing bit 4 of CR1 if you want the OSC to be off in STOP mode.

Yes. An external canned oscillator or square wave can be used to drive the 68HC908GP20, up to a maximum frequency of 32 MHz externally, with the PLL off. With the PLL on, an external clock can be used up to 1.5 MHz external speed.

The two oscillators on the 68HC705L5 are called OSC and XOSC. OSC is the main oscillator and XOSC is the secondary oscillator. Several methods of clock distribution can be used for the 68HC705L5. The Miscellaneous Register (MR) is used to administer the system clock. It provides the following functions.

1. Enable OSC or XOSC to be used as the system clock
2. Turn on and off OSC
3. Select system clock frequencies for OSC and XOSC
4. Select the Option Memory Map. (This will not be discussed.)

For easy reference the MR register is shown here.

Because the system clock can be changed through software, flags must be used to alert when a clock is stable, shut down, or powering up. The FTUP and STUP bits report these situations as they occur.

The FTUP bit is a read-only flag showing the status of OSC. 1 = OSC is stable and is available for the system clock. 0 = OSC is in the midst of a power-on reset and it has been disabled by the F_OSCE bit (0), or the chip is in STOP mode.

The STUP bit is a read-only flag showing the status of XOSC. 1 = XOSC is stable and available for the system clock. 0 = XOSC is not stabilized or there is no connection on the XOSC1 and XOSC2 pins.

The SYS1 and SYS0 bits are read/write pins able to select one of four system clock sources. Refer to Table 6-1 on page 6-6 in the 68HC705L5 Technical Databook.

The F_OSCE bit is a read/write bit that can turn the OSC on or off. 1 = This enables the OSC circuit to start running. After 8072 clocks, an overflow from the POR (power on reset) counter sets the FTUP bit. The OSC is now stable and available to be the system clock. 0 = When OSC is turned off, the FTUP bit is cleared and the POR counter is cleared. The 7-bit prescaler is also cleared. Do not clear this bit when OSC is the system clock.

WARNING:
When writing to the MR register, the chip will get locked up if you change the system clock to XOSC and turn off OSC with the same instruction. For example:

LDA #$0C
STA $3E ;chip will lock up

The proper way to change to XOSC and turn off OSC is:

LDA #$0E
STA $3E ;XOSC is system clock, OSC still running
LDA #$0C
STA $3E ;turn off OSC, F_OSCE=0

The 68HC05L5 has two oscillators: a standard OSC using up to approximately 4 MHz and a slower 32 kHz XOSC. During the STOP Mode, the XOSC does not stop oscillating. It can be used to drive the time base for the LCD driver. Therefore, during STOP Mode when the device is in low-power mode, the LCD driver will still operate keeping the display refreshed and overcoming the problem of the display clearing when STOP is entered.

The XOSC is selected by clearing the TBCLK bit in the TBCR1 register. This bit can be written to only once after reset in the ROM. This is not true for the EPROM part.

The notes for the PLL frequency selection of 4.194 MHz state that this selection is for high-speed MCUs only. This device is not offered as a high-speed part. Therefore, this option should never be selected. A high-speed option is available for the ROM device (MC68HSC05E1).

1. Windowed EPROM MCUs must be covered with opaque tape prior to programming and always when in circuit.
2. The EPROM array was not blank. Yes it's simple, but it happens!
3. The programming voltage (V_PP) was not set correctly. Refer to the MCU databook for the correct programming voltage (varies by MCU). Measure V_PP at the socket/device, not at the board connector.
4. The socket contacts are worn. Motorola's parallel programmers are designed for development work only, not volume programming. Many socket insertions will lead to unreliable operation.
5. The MCUs MOR (mask options register) has options unintentionally enabled. Ensure that the MOR location is programmed with either the appropriate value for the options enabled or $00. This is necessary when using Motorola's parallel programmers since the erased state of an external EPROM (ie 2764) is typically $FF, whereas the erased state of the MOR is typically $00.
6. In addition to programming the MOR as outlined here, users of Motorola's parallel programmers can minimize programming time by ensuring the external EPROM's memory locations that are not used for MCU code be programmed to the erased state of the MCU. Check the device databook, but this is usually $00.

The 68HC05F6 has two external IRQ pins. The BIH and BIL instructions test the state of the IRQ1 pin only and not the IRQ2 pin!

The MCU must be put into boot-load mode to program or verify OTP/EPROM parts on Motorola's parallel programmers. This is done by applying V_PP to the board. Again, this is necessary even if just verifying the MCU contents.

These devices all contain the MCAN module. However, the 68HC705X4 is radically different from the 68HC705X16 and 68HC705X32. The 68HC705X16 and 68HC705X32 are directly derived from the 68HC05B Family while the 68HC705X4 has the more recent core design which always contains the core timer. This has resulted in a very different operation of the COP between these devices.

The 68HC705X4 COP must be cleared by writing a '0' to bit 0 of address $1FF0 using the STA $1FF0 instruction while the 68HC705X16 and 68HC705X32 require a write of '1' to bit 0 of address $000C (the Miscellaneous register). Since the 68HC705X16 and 68HC705X32 have the COP refresh register in page zero it is possible to use BSET 0,$0C.

The COP time-out for the 68HC705X16 and 68HC705X32 is fixed at 4 mS (for 2 MHz bus) while the 68HC705X4 has a choice of approximately 50 mS up to 420 mS for a 2 MHz bus.

Note the different addresses of the MOR for the 68HC705X32 and 68HC705X16.

68HC705X16 MOR address $3DFE

68HC705X32 MOR address $7FDE.

No special part number is required for high-speed 68HC705KJ1 operation. The standard 68HC705KJ1 is specified to operate at the 4 Mhz internal bus speed (500 ns minimum instruction cycle) of other Motorola high-speed OTP versions (68HSC705xx).

The low-power 32 Khz oscillator version of the 68HC705KJ1 is 68HLC705KJ1.

The 68HC705C8A has two COPs (computer operating properly), a programmable COP and a non-programmable COP.

The programmable COP is provided for compatibility with the 68HC705C8. This COP has four different programmable timeout periods, selected by the CM1 and CM0 bits in the Programmable COP Control Register (COPCR, location $001E). The programmable COP is enabled by setting the PCOPE bit in the COPCR. This bit can be set through software once during operation, and it needs to be set again after every hardware reset. The COP counter is reset by writing the values $55 and $AA (in that order) to the COP Reset Register (COPRST, location $001D).

The non-programmable COP is provided for compatibility with the 68HC05C4A. Its timeout period is fixed (262,144/ F_OSC). The non-programmable COP is enabled by setting the NCOPE bit in Mask Option Register 2 (MOR2, location $1FF1). This is an EPROM register, so the value for this bit is permanently programmed. The non-programmable COP counter is reset by writing a logic 0 to bit 0 of address $1FF0.

NOTE: Because the address $1FF0 is not in the first page of memory, the BCLR instruction cannot be used to reset the non-programmable COP. This instruction only works with the direct addressing mode. Use the sequence CLRA, STA $1FF0 to reset this COP.

NOTE: When using the 68HC705C8A, it is possible to have both COPs enabled. If the NCOPE and PCOPE bits are set, then both COPs will be enabled. Both COP counters will need to be reset at the appropriate times. This situation should be avoided.

To characterize devices, it is necessary to subject them to stresses that are repeatable and predictable. This has resulted in the development of three ESD models used to approximate real world ESD events. The first two deal with a charged body discharging to or through an IC to ground, while the third simulates a charged IC discharging to ground.

The Human Body Model (HBM) is used to approximate what happens when a person, charged up to some potential, discharges to or through an IC to ground. In this case, the human body has been modeled as a capacitor of 100 pF, discharging through a series resistance of 1.5 K-Ohms. The real-world situation and the model are depicted in Figure 1. When this capacitor is charged to 2000 V, it can deliver a peak current of 1.33 A to the device under test! This peak occurs only ~10 nsec after the event began!

Figure 1 - Human Body Model (HBM) stressing.

The Charged Device Model (CDM) is very different from both HBM and MM. In this case, the device itself is charged up and discharges to ground. For instance, a device sliding out of a plastic rail will charge up via triboelectric charging if the rail isn't treated with an anti-static coating. An IC has much less capacitance than a human body, typically only a few pF, and only a small amount of charge is needed to increase the potential on a device to several hundred volts (V = Q/C). Any charge built up on the device discharges very quickly because of this small capacitance, as is shown in Figure 2.

Figure 2 - Charged Device Model (CDM) stressing

The most common failure modes indicating an EOS event are open pins, shorted pins, and leaking pins. Figure 1 shows the curve traces for each of these situations on a standard I/O pin. Open pins are the result of bond wires or die metalization which has been vaporized and has fused open. Shorted and resistive pins are usually due to die metalization and oxide melting then reflowing into adjacent metal. Leaky pins can also be due to the reflowing of metal and oxide in and near active areas.

Figure 1. Schematic for a typical I/O pin and the curve traces which could be associated with the pin

The physical failure mechanism which results from an EOS event is greatly dependent on the total energy applied to the pin. Both time and current play roles in determining the total energy. Temperature also can be a factor since it is the act of melting metal and oxide which results in an EOS failure.

Only two failure mechanisms normally are associated with EOS: fused bond wires and fuse die metalization (Figures 2 and 3). The average bond wire for a 68HC05 device is 1 ml in diameter and approximately 60 mils long. A direct current of 1 Amp would be sufficient to fuse a bond wire of this dimension. Higher current pulses of shorter duration also could fuse a bond wire. For example, a 5 Amp, 1 msec pulse would most likely fuse the average bond wire. In both these cases, the energy dissipated is equivalent to the energy absorbed by the bond wire. Simple calculations show that when the temperature necessary to absorb this energy exceeds the melting temperature of the gold bond wire, the wire will fuse.

The second mechanism associated with an EOS event is fusing of die metalization. Typically, these events are extremely high current spikes of short duration (<170 usec). In this event, the heat dissipated on the die is conducted away from metalization through the SiO2 to the substrate. SiO2 is a fairly good thermal conductor. Therefore, the current needed to fuse the die metalization is fairly high, typically around 10 Amps.

Since heat plays a big part in creating the EOS damage, it is important to note that in plastic encapsulated devices, the actual fused metalization may not be visible due to carbonized plastic residue left on the die. This carbonized plastic is the direct result of the locally absorbed energy and its resulting high temperature.

Figure 2. SEM micrograph of a fused bond wire

Figure 3. Optical micrograph of typical EOS damage. Both fused and reflowed metal are evident.

The key difference between EOS and electrostatic discharge (ESD) is the rise time of the energy pulse. Rise times associated with an ESD event are in the 5-20 ns range while the rise times for EOS events tend to be much longer. Failure mechanisms associated with both types of events are strictly due to localized heating. Where the localized heating occurs is key to understanding the failure mechanisms. Damage seen on bond wires and die metalization are typically associated with EOS (slow rise time, high energy) while junction degradation, poly melt filaments, and contact damage are associated with ESD (fast rise time, high energy). Typically, most ESD damage is visible only through deprocessing and SEM inspection. Most EOS damage is visible through an optical microscope.

Usually, a device which has failed to withstand an ESD event will have leaky or shorted pins. Because the stress enters the device through the pad, it stands to reason that the circuitry in closest proximity to this stress will fail first. Figure 3 shows a typical I/O pad configuration, and the curve traces for various types of pin failure modes. It is important to note that the four main failure mechanisms (discussed in the next FAQ) can cause any of these failure modes. Occasionally, high supply current and even functional failures can be seen on ESD failures.

Figure 3 - Schematic of a typical I/O pin and the curve traces of various failure modes

Electrostatic discharge is the application of a short-duration, high-energy pulse to the external leads of an integrated circuit. ESD is often confused with electrical overstress (EOS). While both ESD and EOS failures are the direct result of localized heating, the location of the damage differs. Damage seen on bond wires and die metalization are typically associated with EOS, while junction degradation, contact damage, and gate oxide breaches are more often linked with ESD events. The reason for this difference in failure mechanisms is the rise time and duration of the energy pulse. While ESD events may only take less than a microsecond to happen, EOS events are much slower to occur and typically last much longer.

An electrostatic discharge happens when two objects at different potentials come in contact with one another. Charge is transferred from one body to the other until they are both at the same potential. The time required for this charge transfer to take place can vary and depends on the characteristics of the charged bodies, such as their capacitance and the resistance of the discharge path between them. This charge transfer is referred to as an ESD event.

As mentioned earlier, four main failure mechanisms are associated with ESD events. They are junction degradation, thermal oxide degradation, poly melt filaments and contact damage. All are the direct result of localized heating caused by excessive current. It is important to understand the configuration of the output buffers, and their role in the ESD event. Figure 4 shows a cross section through an I/O pad and output buffers.

Figure 4 - Diagram of a cross-section through an I/O pad, showing output buffers

The high energy pulse which is absorbed by a pin travels through the pn junctions attached to the pad, which are the drains of the output n-channel and p-channel transistors for that pin. As is typical in an ESD event, the voltage applied to the pad exceeds the reverse bias breakdown voltage of the drain junctions. Impact ionization causes high current to flow through the diode. The current (and heat generated) eventually becomes localized due to some non-uniformity in the junction processing or the device lay out (i.e. the contact closest to the energy source). This increase in temperature increases the intrinsic carrier concentration, lowering the resistance along that current path. This becomes a preferential current site. More current flows here, generating more heat, lowering the intrinsic concentration, reducing the resistance, allowing more current to flow, and so on, a positive feedback system.

Contact damage, also called contact spiking, is the result of this particular phenomena. See Figure 5. When the excessive current causes the aluminum to heat beyond its melting point of 660 degrees C, the aluminum, which is positively charged, drifts into the substrate under the influence of the electric field. Eventually, the aluminum dopant reaches through the drain diffusion and into the substrate, shorting the drain/substrate diode and resulting in a pad- V_SS leakage path.

Junction damage can also occur in this scenario. If the heat generated by this localized current flow exceeds the melting point of silicon (1400 degrees C), the silicon will melt and reflow, disrupting the dopant profiles in this region of the pn junction. When the ESD event is over, the silicon recrystallizes, with the n- and p-type dopants mixed up, resulting in poor isolation between p- and n- type regions and a leaky drain/substrate diode. This type of damage is visible only after a decoration etch is performed to highlight areas of damaged silicon. This failure mechanism is usually accompanied by other more visible mechanisms, such as contact spiking.

Figure 5 - Diagram of contact spiking

As mentioned earlier, more than one failure mechanism can be present on an ESD failure. The SEM micrograph in Figure 7 shows several mechanisms which occurred as the result of a single ESD event. The unit in this case has been stripped back to silicon. A spiked contact, poly melt filament "trench" and gate oxide rupture are all present.

Figure 6 - SEM micrograph of poly melt filaments. The unit has been stripped back to reveal polysilicon.

Figure 7 - SEM micrograph showing three ESD failure mechanisms resulting from a single ESD stress. A spiked contact, poly melt trench and gate oxide short are all present.

Electrical overstress (EOS) is the misapplication of excessive voltage or current to the external leads of an integrated circuit. The damage caused by EOS is actually a result of the total energy applied to the device. Externally, the damage will result in open, short or leaking pins. It can also affect the devices functionality. Internally, the result is typically seen as fused bond wires or damage to the die metalization.

Objects charge in a number of ways. Perhaps the most common is through frictional charging, also known as triboelectric charging. This involves the transfer of electrons from one object to another through direct contact. Several factors can affect the efficiency of the charge separation, such as relative humidity. For example, walking across a carpet in summertime when it's humid will not generate much charge, but could develop a signficant charge in wintertime, when humidty is low. The components in your television are in close proximity to the electric field generated by the picture tube. When the TV is switched off, there is a great deal of static electricity on the screen and case. Cracking and popping is also heard. This is the discharge of the field-induced charge that has built up on the various components inside the TV.

EMC stands for electromagnetic compatibility. EMC problems occur in one of two categories: emissions or susceptibility. An MCU design that is affected by external noise sources has a susceptibility problem. An MCU design that is a noise source that affects other circuits is an emissions problem. View application note AN1259, System Design and Layout Techniques for Noise Reduction in MCU-Based Systems and application note AN1263/D, Designing for EMC Compatibility with Single-Chip MCUs for more information.

A PWM signal is a signal with a fixed frequency and variable on and off times. In other words, the period of the signal remains constant, but the amount of time that the signal remains high and low can vary within a period. Such a signal can be generated by using the output compare function of the timer subsystem.

The duty cycle (DC) of a PWM signal is the ratio of on time to the total period (on time + off time). Such signals are useful to control devices or provide a variable DC voltage. Common applications include motor, lighting, and climate controls.

For more information, useful PWM resources are:

application note AN1734/D, Pulse Width Modulation Using the 16-Bit Timer

TIM08RM/AD, M68HC08 TIM08 Timer Interface Module Reference Module

There are several ways to produce PWM signals with Motorola MCUs. Some parts have dedicated PWM circuitry. For example, the (7)05B16 has two PWM channels directly linked to its timer subsystem.

The most convenient method to implement involves the use of the output compare function. Given a desired duty cycle and frequency, one can determine the amount of timer counts necessary to produce the on and off segments that compose a pulse train.

These timer delays can be added to the current timer counter value and stored in the output compare registers. The value of the OLVL (output level) bit in the timer control register determines the logic level which will be output to the TCMP pin on the next valid compare.

Through the OLVL bit, the TCMP pin output level for the next valid compare can be set. When the timer counter reaches the value in the output compare registers, the OLVL bit value is asserted on the TCMP pin, and an interrupt can be triggered. The interrupt can then setup the next output level and delay. In this fashion, a pulse train of varying logic levels and durations can be output through the TCMP pin.

This method is documented in application note AN1734D, Pulse Width Modulation Using the 16-bit Timer.

The 68HC05C4A is our lowest price MCU with hardware asynchronous serial communications (SCI). Software can be used with any 68HC05 to emulate the SCI in cost sensitive applications. Refer to application note AN1240/D, Software driven Asynchronous Serial Communication Techniques.

Two application notes deal with this topic:

AN1298/D, Variations in the 68HC(7)05C Family, This application note compares and contrasts the features of all C Family microcontrollers, including:

• "A" vs. "non-A" parts (e.g. 68HC705C8 vs. 68HC705C8A)
• OTP (one-time programmable) and ROM parts
• Development Tools

AN1226/D, Use of the 68HC705C8A in place of a 68HC705C8,

• This application note specifically addresses considerations of moving from the C8 to the C8A MCU.

The technical data books for the different parts should also be consulted.

There are two compatibility considerations: pin compatibility and code compatibility.

Pin compatibility: Except for the 68HC05C0, the DIP, SDIP, and QFP packages of C-Family parts are pin-for-pin compatible. The PLCC package has minor differences among family members. Consult application note AN1298, page 10 for more details.

Code compatibility: There are some differences in code considerations among the different family members. The differences exist between different C-Family members, OTP and ROM parts, and A and non-A parts. These differences include the COP (computer operating properly) features, MOR (mask option register) programming, and the behavior of the STOP instruction. For more information, consult application note AN1298/D.

• One significant improvement is the increased current drive available on the PC7 port pin (port C, bit 7). This improvement provides LED drive capability. There is no way to reduce the PC7 drive current of the 68HC705C8A to emulate the 68HC705C8.
• Port B pins on the C8A have programmable external interrupt capability, and programmable pull up devices.
• A non-programmable COP (C4A COP) is added to the C8A, in addition to the programmable COP (C8 COP).
• Two additional MOR registers have been added on the 68HC705C8A. These control the non-programmable COP and the port B interrupts/pull-ups.
• An SPI (serial peripheral interface) bug which existed in the 68HC705C8 is fixed in the 68HC705C8A.